- 您现在的位置：买卖IC网 > PDF目录69322 > RJ80530GZ933512 (INTEL CORP) 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479 PDF资料下载
参数资料
| 型号： | RJ80530GZ933512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 36/92页 |
| 文件大小： | 1750K |
| 代理商： | RJ80530GZ933512 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页当前第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
Mobile Intel
Pentium III Processor-M Datasheet
298340-003
Datasheet
41
Table 27. TAP Signal AC Specifications
1
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T30
TCK Frequency
—
16.67 MHz
T31
TCK Period
60
—
ns
6
T32
TCK High Time
25.0
ns
6
≥ V
CMOSREF+0.2V, Note 2
T33
TCK Low Time
25.0
ns
6
≤ V
CMOSREF-0.2V, Note 2
T34
TCK Rise Time
5.0
ns
6
(VCMOSREF-0.2V) –
(VCMOSREF+0.2V),
Notes 2, 3
T35
TCK Fall Time
5.0
ns
6
(VCMOSREF+0.2V) –
(VCMOSREF-0.2V),
Notes 2, 3
T36
TRST# Pulse Width
40.0
ns
16
Asynchronous, Note 2
T37
TDI, TMS Setup Time
5.0
ns
15
Note 4
T38
TDI, TMS Hold Time
14.0
ns
15
Note 4
T39
TDO Valid Delay
1.0
10.0
ns
15
Notes 5, 6
T40
TDO Float Delay
25.0
ns
15
Notes 2, 5, 6
T41
All Non-Test Outputs Valid Delay
2.0
25.0
ns
15
Notes 5, 7, 8
T42
All Non-Test Outputs Float Delay
25.0
ns
15
Notes 2, 5, 7, 8
T43
All Non-Test Inputs Setup Time
5.0
ns
15
Notes 4, 7, 8
T44
All Non-Test Inputs Hold Time
13.0
ns
15
Notes 4, 7, 8
NOTES:
1.
All AC timings for TAP signals are referenced to the TCK rising edge at 1.0V. All TAP and CMOS signals are
referenced at 1.0V.
2.
Not 100% tested. Specified by design/characterization.
3.
1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
4.
Referenced to TCK rising edge.
5.
Referenced to TCK falling edge.
6.
Valid delay timing for this signal is specified into 150
terminated to 1.5V and 0 pF of external load. For real
system timings these specifications must be derated for external capacitance at 105 ps/pF.
7.
Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and TMS).
These timings correspond to the response of these signals due to boundary scan operations.
8.
During Debug Port operation use the normal specified timings rather than the TAP signal timings.
Table 28. Quick Start/Deep Sleep AC Specifications
1
Symbol
Parameter
Min Max
Unit
Figure
Notes
T45
Quick Start Cycle Completion to Clock Stop or
DPSLP# assertion
100
BCLKs 17, 18
T46
Quick Start Cycle Completion to Input Signals Stable
0
s
17, 18
T47
Deep Sleep PLL Lock Latency
0
30
s
17, 18
Note 2
T48
STPCLK# Hold Time from PLL Lock
0
ns
17, 18
T49
Input Signal Hold Time from STPCLK# Deassertion
8
BCLKs 17, 18
NOTES:
1.
Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2.
The BCLK, BCLK# Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
相关PDF资料 |
PDF描述 |
|---|---|
| RJ80536VC001512M | 1000 MHz, MICROPROCESSOR, PBGA479 |
| RJ80536NC0211M | 1500 MHz, MICROPROCESSOR, PBGA479 |
| RK80530KZ006512 | 32-BIT, 1133 MHz, MICROPROCESSOR, CPGA370 |
| RK80530KZ017512 | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA370 |
| RK80532EC056512 | 2400 MHz, MICROPROCESSOR, CPGA604 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RJ80530KZ001512 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述: |
| RJ80530KZ001512S L6QU | 制造商:Intel 功能描述:32BIT MPU 80530KZ001512 1.00G |
| RJ80530KZ800512 | 制造商:Rochester Electronics LLC 功能描述:PIII PROCESSOR LV, 800MHZ, 512K, PBGA - Bulk |
| RJ80530KZ800512S L66D | 制造商:Intel 功能描述:MPU Pentium? III Processor-S 32-Bit 0.13um 800MHz 479-Pin uFCBGA |
| RJ80530KZ800512S L6HC | 制造商:Intel 功能描述:MPU Pentium? III Processor-S 0.13um 800MHz 479-Pin uFCBGA |
发布紧急采购，3分钟左右您将得到回复。