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参数资料
型号： RJ80530GZ933512
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479
封装： MICRO, FCBGA-479
文件页数： 84/92页
文件大小： 1750K
代理商： RJ80530GZ933512
Mobile Intel
Pentium III Processor-M Datasheet
298340-003
Datasheet
85
without glitches, from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (1.8V) state. Figure 12 through
Figure 14 illustrate the relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before the rising edge of PWRGOOD.
It must also meet the minimum pulse width specified in Table 24 (Section 3.7) and be followed by a
1 ms RESET# pulse. PWRGOOD may be asserted before BCLK is active (please refer to Table 24,
Note 5).
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD signal should be driven high throughout boundary
scan operation.
REQ[4:0]# (I/O - AGTL)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on both
agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]# to define
the currently active transaction type.
RESET# (I - AGTL)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2
caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must stay
active for at least 1 ms after VCC and BCLK, BCLK# have reached their proper DC and AC
specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus agents
will deassert their outputs within two clocks. RESET# is the only AGTL signal that does not have on-
die AGTL termination. A 56.2
1% terminating resistor connected to VCCT is required.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-on
configuration. The configuration options are described in Section 4 and in the P6 Family of Processors
Developer’s Manual.
Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition of
RESET#, the processor optionally executes its built-in self-test (BIST) and begins program execution
at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the appropriate pins/balls
on both agents on the system bus.
RP# (I/O - AGTL)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the
system bus.
A correct parity signal is high if an even number of covered signals is low and low if an odd number of
covered signals are low. This definition allows parity to be high when all covered signals are high.
RS[2:0]# (I/O - AGTL)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
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