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参数资料
| 型号： | RJ80530GZ933512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 81/92页 |
| 文件大小： | 1750K |
| 代理商： | RJ80530GZ933512 |
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Mobile Intel
Pentium III Processor-M Datasheet
82
Datasheet
298340-003
DRDY# (I/O - AGTL)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid
data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle clocks.
This signal must be connected to the appropriate pins/balls on both agents on the system bus.
DPSLP# (I - 1.5V Tolerant)
The DPSLP# (Deep Sleep) signal, when asserted in the Quick Start state, causes the processor to enter
the Deep Sleep state. In order to return to the Quick Start state BCLK, BCLK# must be running and
the DPSLP# pin must be deasserted.
EDGCTRLP (I-Analog)
The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the AGTL output
buffers. Connect the signal to VSS with a 110-, 1% resistor.
FERR# (O - 1.5V Tolerant Open-drain)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it is included for
compatibility with systems using DOS-type floating-point error reporting.
FLUSH# (I - 1.5V Tolerant)
When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache lines in
the Modified state and invalidates all internal cache lines. At the completion of a flush operation, the
processor issues a Flush Acknowledge transaction. The processor stops caching any new data while the
FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to
determine its power-on configuration.
GHI# (I - 1.25V)
The GHI# signal controls the selection of the operating mode bus ratio in a Mobile Intel Pentium III
Processor-M. This signal is latched on exit from the Deep Sleep state and determines which of two bus
ratios is selected for operation. This signal is ignored when the processor is not in the Deep Sleep state.
This signal has an on-die pull-up to VCCT and should be driven with an Open-drain driver with no
external pull-up.
HIT# (I/O - AGTL), HITM# (I/O - AGTL)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results,
and must be connected to the appropriate pins/balls on both agents on the system bus. Either bus agent
can assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
IERR# (O - 1.5V Tolerant Open-drain)
The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus. This
transaction may optionally be converted to an external error signal (e.g., NMI) by system logic. The
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