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参数资料
| 型号： | RJ80530GZ933512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 83/92页 |
| 文件大小： | 1750K |
| 代理商： | RJ80530GZ933512 |
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Mobile Intel
Pentium III Processor-M Datasheet
84
Datasheet
298340-003
NC (No Connect)
All signals named NC (No Connect) must be left unconnected.
NCTRL (I - Analog)
The NCTRL signal provides the AGTL pull down impedance control. The processor samples this
input to determine the N-channel pull-down device strength when it is the driving agent. An external
14 ohm (1% tolerance) pull-up resistor to VCCT is required for this signal. Please refer to platform
design guide for implementation details.
NMI (I - 1.5V Tolerant)
The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI
becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an
internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated. If
NMI is asserted during the execution of an NMI service routine, it remains pending and is recognized
after the IRET is executed by the NMI service routine. At most, one assertion of NMI is held pending.
NMI is rising edge sensitive.
PICCLK (I – 2.0V Tolerant)
The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC that
is required for operation of the processor, system logic, and I/O APIC components on the APIC bus.
PICD[1:0] (I/O - 1.5V Tolerant Open-drain)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC
bus. They must be connected to the appropriate pins/balls of all APIC bus agents, including the
processor and the system logic or I/O APIC components. If the PICD0 signal is sampled low on the
active-to-inactive transition of the RESET# signal, then the APIC is hardware disabled. For the
Mobile Intel Pentium III Processor-M, the APIC is required to be hardware enabled as described in
Section 7.1.3
PLL1, PLL2 (Analog)
The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL. See
Section 3.2.2 for a description of the analog decoupling circuit.
PRDY# (O - AGTL)
The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor
debug readiness.
PREQ# (I - 1.5V Tolerant)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processor.
PWRGOOD (I – 1.8V Tolerant)
PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a clean
indication that clocks and the power supplies (VCC, VCCT, etc.) are stable and within their
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current) and
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