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| 型号： | RJ80530GZ933512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 51/92页 |
| 文件大小： | 1750K |
| 代理商： | RJ80530GZ933512 |
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Mobile Intel
Pentium III Processor-M Datasheet
298340-003
Datasheet
55
reliability of the processor. The overshoot and undershoot specifications for non AGTL signals are
Table 35. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core
Allowed Pulse Duration (ns) [Tj=100C]
Max VCmos + Overshoot/Undershoot
Magnitude (volts)
Activity Factor = 0.01
Activity Factor = 0.1
Activity Factor = 1
2.38
6.5
0.65
0.065
2.33
13
1.3
0.13
2.28
29
2.9
0.29
2.23
60
6
0.6
2.18
60
12
1.2
2.13
60
26
2.6
2.08
60
56
5.6
NOTES:
1.
VCMOS(nominal) = 1.5V.
2.
Under no circumstances should the sum of the Max VCMOS and absolute value of the Overshoot/Undershoot
voltage exceed 2.38V.
3.
Activity factor of 1 represents a toggle rate of 33 MHz.
4.
System designers are encouraged to follow Intel provided non-AGTL layout guidelines.
5.
All values are specified by design characterization, and are not tested.
4.3.1
PWRGOOD, VTTPWRGD Signal Quality Specifications
The processor requires PWRGOOD to be a clean indication that clocks and the power supplies (VCC,
VCCT, etc.) are stable and within their specifications. Clean implies that the signal will remain below
VIL18 and without errors from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (1.8V) state. The VTTPWRGD
signal must also transition monotonically.
The VTTPWRGD signal is an input to the processor used to determine that the VTT power is stable
and the VID and BSEL signals should be driven to their final state by the processor. To ensure the
processor correctly reads this signal, it must meet the following requirement while the signal is in its
transition region of 300 mV to 900 mV. Also, VTTPWRGD should only enter the transition region
once, after VTT is at nominal values, for the assertion of the signal.
4.3.1.1
VTTPWRGD Noise Parameter Specification
Parameter
Specification
Amount of noise (glitch)
Less than 100 mV
In addition, the VTTPWRGD signal should have reasonable transition time through the transition
region. A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this
signal. Intel recommends the following transition time for the VTTPWRGD signal.
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