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参数资料
| 型号： | RJ80530GZ933512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 79/92页 |
| 文件大小： | 1750K |
| 代理商： | RJ80530GZ933512 |
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Mobile Intel
Pentium III Processor-M Datasheet
80
Datasheet
298340-003
wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is
activated on specific clock edges and sampled on specific clock edges.
BP[3:2]# (I/O - AGTL)
The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are outputs
from the processor that indicate the status of breakpoints.
BPM[1:0]# (I/O - AGTL)
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They
are outputs from the processor that indicate the status of breakpoints and programmable counters used
for monitoring processor performance.
BPRI# (I - AGTL)
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the system bus. It must
be connected to the appropriate pins/balls on both agents on the system bus. Observing BPRI# active
(as asserted by the priority agent) causes the processor to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of
its requests are completed and then releases the bus by deasserting BPRI#.
BREQ0# (I/O - AGTL)
The BREQ0# (Bus Request) signal is a processor Arbitration Bus signal. The processor indicates that it
wants ownership of the system bus by asserting the BREQ0# signal.
During power-up configuration, the central agent must assert the BREQ0# bus signal. The processor
samples BREQ0# on the active-to-inactive transition of RESET#. Optionally, this signal may be
grounded with a 10- resistor.
BSEL[1:0] (O – 3.3V Tolerant)
The BSEL[1:0] (Select Processor System Bus Speed) signal is used to configure the processor for the
system bus frequency. The chipset and system clock generator also uses the BSEL signals. The
VTTPWRGD signal informs the processor to output the BSEL signals. During power up the BSEL
signals will be indeterminate for a small period of time. The chipset and clock generator should not
sample the BSEL signals until the VTTPWRGD signal is asserted. The assertion of the VTTPWRGD
signal indicates that the BSEL signals are stable and driven to a final state by the processor. Please
refer to Figure 12 for the timing relationship between the BSEL and VTTPWRGD signals.
Table 44 shows the encoding scheme for BSEL[1:0]. The only supported system bus frequency for the
Mobile Intel Pentium III Processor-M is 133 MHz. The Low Voltage Mobile Intel Pentium III
Processor-M will support both 100-MHz and 133-MHz bus frequencies. The Ultra Low Voltage
Mobile Intel Pentium III Processor-M will support both 100-MHz and 133-MHz bus frequencies (see
product features for specific supported frequencies). If another frequency is used then the processor is
not guaranteed to function properly.
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