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参数资料
| 型号： | RK80532KE056512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2400 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO, PGA2-604 |
| 文件页数： | 64/102页 |
| 文件大小： | 1464K |
| 代理商： | RK80532KE056512 |
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64
Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
FERR#/PBE#
O
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and
its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/
PBE# indicates a floating-point error and will be asserted when the processor
detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/
PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included
for compatibility with systems using MS-DOS*-type floating-point error reporting.
When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal state. For
additional information on the pending break event functionality, including the
identification of support of the feature and enable/disable information, refer to
volume 3 of the Intel Architecture Software Developer's Manual and the Intel
Processor Identification and the CPUID Instruction application note.
This signal does not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
3
GTLREF
I
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3Vcc. GTLREF is used by the AGTL+ receivers to determine if a
signal is a logical 0 or a logical 1.
HIT#
HITM#
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any front side bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting HIT#
and HITM# together.
Since multiple agents may deliver snoop results at the same time, HIT# and HITM#
are wire-OR signals which must connect the appropriate pins of all processor front
side bus agents. In order to avoid wire-OR glitches associated with simultaneous
edge transitions driven by multiple drivers, HIT# and HITM# are activated on
specific clock edges and sampled on specific clock edges.
4
IERR#
O
IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
processor front side bus. This transaction may optionally be converted to an
external error signal (e.g., NMI) by system core logic. The processor will keep
IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
This signal does not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
3
IGNNE#
I
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
3
INIT#
I
INIT# (Initialization), when asserted, resets integer registers inside all processors
without affecting their internal caches or floating-point registers. Each processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins
of all processor front side bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
3
Table 41. Signal Definitions (Sheet 5 of 9)
Name
Type
Description
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| BX80532KE3060D | 3060 MHz, MICROPROCESSOR, XMA |
| BX80532KE2400DU | 2400 MHz, MICROPROCESSOR, XMA604 |
| RK80532PG072512 | 2800 MHz, MICROPROCESSOR, PGA478 |
| RK80532RC049128 | 32-BIT, 2100 MHz, MICROPROCESSOR, CPGA478 |
| RK80532RC056128 | 2400 MHz, MICROPROCESSOR, CPGA478 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80532KE056512S L6GD | 功能描述:IC XEON 2.4GHZ INT-MPGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| RK80532KE056512S L6VL | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:PRESTONIA; MPU XEON NETBURST 64BIT 0.13UM 2.4GHZ 604PIN - Trays |
| RK80532KE056512S L72D | 制造商:Intel 功能描述:MPU Xeon? Processor 64-Bit 0.13um 2.4GHz 604-Pin FCPGA |
| RK80532KE056512SL73L | 功能描述:IC XEON 2.4GHZ 604FC-MPGA-2P RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| RK80532KE067512 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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