参数资料
型号: RK80532KE056512
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 2400 MHz, MICROPROCESSOR, CPGA604
封装: FLIP CHIP, MICRO, PGA2-604
文件页数: 77/102页
文件大小: 1464K
代理商: RK80532KE056512
76
Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz
6.2.2
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of BINIT#, INIT#, LINT[1:0]
(NMI, INTR), or an interrupt delivered over the front side bus. RESET# will cause the processor to
immediately initialize itself.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
6.2.3
Stop-Grant State—State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once
the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop
Grant state. Both logical processors of the Intel Xeon processor with 533 MHz Front Side Bus
must be in the Stop Grant state before the deassertion of STPCLK#.
Figure 22. Stop Clock State Machine
2. Auto HALT Power Down
State
BCLK running
Snoops and interrupts allowed
1. Normal State
Normal execution
4. HALT/Grant Snoop State
BCLK running
Service snoops to caches
3. Stop Grant State
BCLK running
Snoops and interrupts allowed
5. Sleep State
BCLK running
No snoops or interrupts
allowed
HALT Instruction and
HALT Bus Cycle Generated
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI,
RESET#
STPCLK#
Asserted
STPCLK#
De-asserted
STP
CLK
#As
sert
ed
STP
CLK
#D
e-as
serted
SLP#
Asserted
SLP#
De-asserted
Snoop Event Occurs
Snoop Event Serviced
.
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