参数资料
型号: RK80532KE056512
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 2400 MHz, MICROPROCESSOR, CPGA604
封装: FLIP CHIP, MICRO, PGA2-604
文件页数: 76/102页
文件大小: 1464K
代理商: RK80532KE056512
Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz
75
6.0
Features
6.1
Power-On Configuration Options
The Intel Xeon Processor with 533 MHz Front Side Bus has several configuration options that
are determined by the state of specific processor pins at the active-to-inactive transition of the
processor RESET# signal. These configuration options cannot be changed except by another reset.
Both power on and software induced resets reconfigure the processor(s).
NOTES:
1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option.
2. The Intel Xeon processor with 533 MHz Front Side Bus does not support this feature, therefore platforms
utilizing this processor should not use these configuration pins.
3. Intel Xeon processor with 533 MHz Front Side Bus utilize only BR0# and BR1# signals. 2-way platforms must
not utilize BR2# and BR3# signals.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 22 for a visual representation of the processor low power states.
Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the
other processor in the Normal or Stop-Grant state.
6.2.1
Normal State—State 1
This is the normal operating state for the processor.
Table 43. Power-On Configuration Option Pins
Configuration Option
Pin1
Notes
Output tri state
SMI#
Execute BIST (Built-In Self Test)
INIT#
In Order Queue de-pipelining (set IOQ depth to 1)
A7#
Disable MCERR# observation
A9#
Disable BINIT# observation
A10#
APIC cluster ID (0-3)
A[12:11]#
2
Disable bus parking
A15#
Disable Hyper-Threading Technology
A31#
Symmetric agent arbitration ID
BR[3:0]#
3
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