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| 型号： | RM7965A-900UI |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 900 MHz, MICROPROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256 |
| 文件页数： | 11/60页 |
| 文件大小： | 508K |
| 代理商： | RM7965A-900UI |
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
19
Document No.: PMC-2100294, Issue 2
Note that integer multiply/divide instructions, as well as their corresponding MFHi and MFLo
instructions, can only be executed in the F pipe execution unit. Within each execution unit, the
operational characteristics are the same as on previous MIPS designs with single cycle ALU
operations (add, sub, logical, shift), one cycle load delay, and an autonomous multiply/divide
unit.
4.6.1
Register File
The E9000 has 32 general-purpose registers with register location 0 (r0) hard wired to a zero
value. These registers are used for scalar integer operations and address calculation. In order to
service the two integer execution units, the register file has four read ports and two write ports
and is fully bypassed both within and between the two execution units to minimize operation
latency in the pipeline.
4.7
Integer ALU
The E9000 has two complete integer ALUs each consisting of an integer adder/subtractor, a
logic unit, and a shifter. Table 4 shows the functions performed by the ALUs for each execution
unit. Each of these units is optimized to perform all operations in a single processor cycle.
Table 4 Integer ALU Operations
Unit
F Pipe
M Pipe
Adder
add, sub
add, sub, data address add
Logic
logic, moves, zero shifts (nop)
Shifter
non-zero shift
non-zero shift, store align
4.8
Integer Multiply/Divide
The E9000 has a single dedicated integer multiply/divide unit optimized for high-speed multiply
and multiply-accumulate operations. The multiply/divide unit resides in the F pipe execution
unit. Table 5 shows the performance of the multiply/divide unit on each operation.
Table 5 Integer Multiply/Divide Operations
Opcode
Operand Size
Latency
Repeat Rate
Stall Cycles
16 bit
4
3
0
MULT/U, MAD/U
32 bit
5
4
0
16 bit
4
3
2
MUL
32 bit
5
4
3
DMULT, DMULTU
any
9
8
0
DIV, DIVD
any
36
0
DDIV, DDIVU
any
68
0
MSUB, MSUBU
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