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参数资料
| 型号： | RM7965A-900UI |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 900 MHz, MICROPROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256 |
| 文件页数： | 3/60页 |
| 文件大小： | 508K |
| 代理商： | RM7965A-900UI |
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
11
Document No.: PMC-2100294, Issue 2
2
Introduction
The RM7965A is a high-performance 64-bit microprocessor with features including a seven-
stage dual-issue pipeline, tightly coupled L1 and L2 caches, and sophisticated branch prediction
for maintaining pipeline efficiency.
A 200 MHz 64-bit multiplexed system address and data bus (SysAD) enables a high-bandwidth
I/O interface to a variety of system controllers providing connectivity to a wide range of
networking peripherals. The RM7965A also contains a vectored and prioritized interrupt
controller for versatile interrupt configurations.
On-chip EJTAG debug modules ensure smooth and easy debugging hardware and software by
allowing both single-step and state examination. The inclusion of a pipeline-rate branch
instruction trace buffer facilitates debugging under operating conditions.
2.1
Features
CPU core with MIPS64-compatible Instruction Set Architecture that features:
o
900 MHz operation.
o
Dual-issue superscalar 7-stage pipeline.
o
16-KB, 4-way set associative L1 Instruction cache.
o
16-KB, 4-way set associative L1 Data cache.
o
256-KB, 4-way set associative L2 cache with industry best 5-cycle access latency.
o
Error Checking and Correcting (ECC) on L2 cache.
o
Fast Packet Cache to assist processing of packet data.
o
8K-entry branch prediction table.
o
Fully associative 64-entry TLB with dual pages.
o
High performance Floating Point unit (IEEE 754).
o
Fixed-point DSP instructions such as Multiply/Add, Multiply/Subtract, and 3 Operand
Multiply.
High-performance system interface:
o
Multiple outstanding reads with out of order return.
o
1600 MB/s peak throughput.
o
200 MHz maximum frequency using HSTL signaling on the SysAD bus.
o
Multiplexed address/data bus (SysAD) supports 1.5 V, 2.5 V, and 3.3 V I/O logic.
o
Processor clock multipliers 2, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9, 10, 11, 12,
13, 14, 15, 16, 17.
Integrated on-chip EJTAG controller.
64-entry dynamic Trace Buffer for use in real-time trace and debug.
Two 32-bit virtually addressed Watch registers.
Integrated performance counters:
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