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参数资料
| 型号： | RM7965A-900UI |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 900 MHz, MICROPROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256 |
| 文件页数： | 29/60页 |
| 文件大小： | 508K |
| 代理商： | RM7965A-900UI |
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Downloaded
[controlled]
by
Venkatesh
Betageri
of
IHS
on
Wednesday,
12
January,
2011
02:34:04
AM
RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
35
Document No.: PMC-2100294, Issue 2
Cache Coherency
Attribute
Read miss
to MM
Store Hit
Store Miss
L2
110: Uncached Non-
Blocking; Uncached.
Reads do not stall
pipeline unless a data
dependency exists.
Strong ordering not
enforced, therefore loads
can be completed out of
program order
-
111: Bypass (Fast
Packet Cache); Bypass
L2
Fill L1
Store L1
Fill L1, Store L1
Bypassed
5.5
Cache Attributes
The RM7965A cache attributes for the instruction, data and internal secondary caches are
summarized in Table 14.
Table 14 RM7965A Cache Attributes
Attribute
Primary Instruction
Primary Data
On-chip Secondary
Size
16 KB
256 KB
Associativity
4-way
Replacement
Algorithm
cyclic
Line size
32 byte
Index
vAddr11..0
pAddr15..0
Tag
pAddr35..12
pAddr35..16
Write policy
N/A
write-back, write-through
block write-back, bypass
Read policy
N/A
non-blocking
(2 outstanding)
non-blocking (data only, 2
outstanding)
Read order
critical word first
Write order
N/A
sequential
Miss restart
following
complete line
first double (if waiting for
data)
N/A
Protection
per word parity
per byte parity
8-bit ECC per DW
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