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参数资料
| 型号： | RM7965A-900UI |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 900 MHz, MICROPROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256 |
| 文件页数： | 30/60页 |
| 文件大小： | 508K |
| 代理商： | RM7965A-900UI |
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Downloaded
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Venkatesh
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of
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on
Wednesday,
12
January,
2011
02:34:04
AM
RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
36
Document No.: PMC-2100294, Issue 2
5.6
Cache Locking
The E9000 core in the RM7965A product allows critical code or data fragments to be locked
into the primary and secondary caches. The user has complete control over the locking function.
For instruction and data fragments in the primary caches, locking is accomplished by setting
either or both of the cache lock enable bits and specifying the set in the CP0 ECC register, then
executing either a load instruction for data, or a Fill_I cache operation for instructions.
Only cache lines within sets A and B of each cache can be locked. Locking within the secondary
works identically to the primaries using a separate secondary lock enable bit and the same set
selection field. As with the primaries, only sets A and B can be locked. Table 15 summarizes the
cache locking capabilities.
Table 15 Cache Locking Control
Cache
Lock Enable
Set Select
Activate
Primary I
ECC[27]
ECC[28]=0A
ECC[28]=1B
Fill_I
Primary D
ECC[26]
ECC[28]=0A
ECC[28]=1B
Load/Store
Secondary
ECC[25]
ECC[28]=0A
ECC[28]=1B
Fill_I or
Load/Store
5.7
Primary Write Buffer
Writes to secondary cache or external memory, whether cache miss write-backs or stores to
uncached or write-through addresses, use the integrated primary write buffer. The write buffer
holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache write-
back and allows the processor to proceed in parallel with memory update. For uncached and
write- through stores, the write buffer significantly increases performance by decoupling the
SysAD bus transfers from the instruction execution stream.
5.8
Data Prefetch
The E9000 supports the MIPS IV integer data prefetch (PREF) and floating-point data prefetch
(PREFX) instructions. These instructions are used by the compiler or by an assembly language
programmer when it is known or suspected that an upcoming data reference is going to miss in
the cache. By appropriately placing a prefetch instruction, the memory latency can be hidden
under the execution of other instructions. In cases where the execution of a prefetch instruction
would cause a memory management or address error exception the prefetch is treated as a NOP.
The “Hint” field of the data prefetch instruction is used to specify the action taken by the
instruction. The instruction can operate normally (that is, fetching data as if for a load operation)
or it can allocate and fill a cache line with zeroes on a primary data cache miss.
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