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参数资料
| 型号： | RM7965A-900UI |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 900 MHz, MICROPROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256 |
| 文件页数： | 45/60页 |
| 文件大小： | 508K |
| 代理商： | RM7965A-900UI |
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62
XMEGA A3U [DATASHEET]
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
LDS
Rd, k
Load Direct from data space
Rd
(k)
None
2
LD
Rd, X
Load Indirect
Rd
(X)
None
1
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X
(X)
X + 1
None
1
LD
Rd, -X
Load Indirect and Pre-Decrement
X
X - 1,
Rd
(X)
X - 1
(X)
None
2
LD
Rd, Y
Load Indirect
Rd
(Y)
(Y)
None
1
LD
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
(Y)
Y + 1
None
1
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
Y - 1
(Y)
None
2
LDD
Rd, Y+q
Load Indirect with Displacement
Rd
(Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd
(Z)
None
1
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
(Z),
Z+1
None
1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
Z - 1,
(Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd
(Z + q)
None
2
STS
k, Rr
Store Direct to Data Space
(k)
Rd
None
2 (1)
ST
X, Rr
Store Indirect
(X)
Rr
None
1 (1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
Rr,
X + 1
None
1 (1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
X - 1,
Rr
None
2 (1)
ST
Y, Rr
Store Indirect
(Y)
Rr
None
1 (1)
ST
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
Rr,
Y + 1
None
1 (1)
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
Y - 1,
Rr
None
2 (1)
STD
Y+q, Rr
Store Indirect with Displacement
(Y + q)
Rr
None
2 (1)
ST
Z, Rr
Store Indirect
(Z)
Rr
None
1 (1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
Rr
Z + 1
None
1 (1)
ST
-Z, Rr
Store Indirect and Pre-Decrement
Z
Z - 1
None
2 (1)
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q)
Rr
None
2 (1)
LPM
Load Program Memory
R0
(Z)
None
3
LPM
Rd, Z
Load Program Memory
Rd
(Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
(Z),
Z + 1
None
3
ELPM
Extended Load Program Memory
R0
(RAMPZ:Z)
None
3
ELPM
Rd, Z
Extended Load Program Memory
Rd
(RAMPZ:Z)
None
3
ELPM
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
(RAMPZ:Z),
Z + 1
None
3
SPM
Store Program Memory
(RAMPZ:Z)
R1:R0
None
-
SPM
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
R1:R0,
Z + 2
None
-
Mnemonics
Operands
Description
Operation
Flags
#Clocks
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