参数资料
型号: RM7965A-900UI
厂商: PMC-SIERRA INC
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 900 MHz, MICROPROCESSOR, PBGA256
封装: 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256
文件页数: 9/60页
文件大小: 508K
代理商: RM7965A-900UI
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
17
Document No.: PMC-2100294, Issue 2
4.3.2
E9000 Pipeline Stages
In contrast to the RM7000 pipeline, the E9000 pipeline has two additional stages to allow an
extra clock cycle of for both the instruction and the data pipeline regimes. The E9000 pipeline
stages can be summarized as follows:
I: Instruction Addressing
C: Instruction Cache Access
R: Register File Access, Instruction Decode
A: Instruction Execution, Data Address Calculation
D: Data Cache Access
M: Data Bus, Data Alignment
W: Write Back to register file
The pipeline execution diagram for the E9000 is shown below:
Figure 4 Pipeline Execution Diagram
I
C
R
I
C
R
A
D
M
MAC1 MAC2 MAC3
A
D
M
W
M-Pipe
F-Pipe
F1
F2
F3
F4
F5
Fetch and Dispatch
(2 instructions per cycle)
Simple Integer Unit
with L/S Unit
Integer MAC Unit
Simple Integer Unit
Floating-point MAC Unit
Floating-point Div/Sqrt Unit
(Iterative)
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