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| 型号： | RM7965A-900UI |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 900 MHz, MICROPROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256 |
| 文件页数： | 21/60页 |
| 文件大小： | 508K |
| 代理商： | RM7965A-900UI |
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
28
Document No.: PMC-2100294, Issue 2
In addition to programmable priority levels, the RM7965A also permits the spacing between
interrupt vectors to be programmed. For example, the minimum spacing between two adjacent
vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set
up the vectors as jumps to the actual interrupt service routines or, if interrupt latency is not
paramount, to include the entire interrupt service routine at one vector. Table 12 illustrates the
complete set of vector spacing selections along with the coding as required in the Interrupt
Control register bits [4:0], ICR.
In general, the active interrupt priority, combined with the spacing setting, generates a vector
offset, which is then added to the interrupt base address of 0x200 to generate the interrupt
exception offset. This offset is then added to the exception base to produce the final interrupt
vector address.
Table 12 Interrupt Vector Spacing
ICR[4:0]
Spacing
0x0
0x000
0x1
0x020
0x2
0x040
0x4
0x080
0x8
0x100
0x10
0x200
others
reserved
4.20 Standby Mode
The RM7965A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
Executing the WAIT instruction enables interrupts and causes the processor to enter Standby
Mode. If the SysAD bus is currently idle when the WAIT instruction completes the W pipe
stage, the internal processor clock stops, thereby freezing the pipeline. The phase lock loop, or
PLL, internal timer/counter, and the "wake up" input pins: INT[9:0]*, NMI*, ExtReq*,
Reset*, and ColdReset* continue to operate in their normal fashion.
If the SysAD bus is not idle when the WAIT instruction completes the W pipe stage, then the
WAIT is treated as a NOP. Once the processor is in Standby, any interrupt, including the
internally generated Timer Interrupt, causes the processor to exit Standby and resume operation
where it left off. The WAIT instruction is typically inserted in the idle loop of the operating
system or real time executive.
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