
Downloaded
[controlled]
by
Venkatesh
Betageri
of
IHS
on
Wednesday,
12
January,
2011
02:34:04
AM
RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
23
Document No.: PMC-2100294, Issue 2
In the control space, the E9000 supports three new registers to support the 64-entry branch
Trace Buffer: Trace Buffer Control and Status (TB CSR), Trace Buffer Out (TB Out), and Trace
Buffer Index (TB IDX). See Section
7.1 Figure 5 CP0 Registers
0
TLB
(entries protected
from TLBWR)
Used for memory
management
* Register number
EntryHi
10*
EntryLo0
2*
EntryLo1
3*
PageMask
5*
47/63
PRId
15*
Wired
6*
Info
7*
Random
1
Index
0
Config
16*
TagHi
29*
TagLo
28*
LLAddr
17*
Used for exception
(set1)
TB CSR
22*
TB Out
23*
TB IDX
24*
Status
12*
EPC
14*
Count
9*
Context
4*
ECC
26*
EJTAG Debug
23*
Cause
13*
Comp are
11*
Watch1
18*
CacheErr
27*
BadVAddr
8*
processing
EJTAG DEPC
24*
ErrorEPC
30*
Perf Ctr Cntrl
22*
Perf Counter
25*
Watch Mask
21
EJTAG Desave
31*
IntControl
20*
IPLHI
19*
IPLLO
18*
DErrAddr0
26*
DErrAddr1
27*
XContext
20*
Watch2
19*
4.14 Memory Management Unit (MMU)
The E9000 has an MMU with a 64 entry TLB, with each entry having dual pages for a total of
128 pages. The page size is programmable to be 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 16 MB,
64 MB, or 256 MB. Pages can be programmed to be write-protected. The TLB can operate
statically or in a demand-paged environment, with TLB misses generating exceptions to load
the appropriate page. The TLB replacement algorithm is random, and there is a TLB fence that
can be used to lock a subset of the TLB entries, and allow the remainder to be dynamically
refilled. The MMU architecture on the E9000 supports both 32 and 64-bit virtual addressing.