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参数资料
| 型号： | ST72F652R4T1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, TQFP-64 |
| 文件页数： | 129/160页 |
| 文件大小： | 974K |
| 代理商： | ST72F652R4T1 |
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ST7265
70/160
USB INTERFACE (Cont’d)
Bits 2:0 = ERR[2:0]
Error type.
These bits identify the type of error which oc-
curred:
Note: These bits are set by hardware when an er-
ror interrupt occurs and are reset automatically
when the error bit (ISTR bit 4) is cleared by soft-
ware.
ENDPOINT 0 REGISTER (EP0R)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 0. It is
also reset by a USB reset, either received from the
USB or forced through the FRES bit in CTLR.
Bit 7 = CTR0
Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed on Endpoint 0. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR on Endpoint 0
1: Correct transfer on Endpoint 0
Bit 6 = DTOG_TX
Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware on recep-
tion of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from
the
USB
host.
DTOG_TX
and
also
DTOG_RX are normally updated by hardware, on
receipt of a relevant PID. They can be also written
by the user, both for testing purposes and to force
a specific (DATA0 or DATA1) token.
Bits 5:4 = STAT_TX [1:0]
Status bits, for transmis-
sion transfers.
These bits contain the information about the end-
point status, as listed below:
Table 18. Transmission Status Encoding
These bits are written by software. Hardware sets
the STAT_TX and STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint; this allows software to prepare the
next set of data to be transmitted.
Bit 3 = Reserved, forced by hardware to 0.
Bit 2 = DTOG_RX
Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
ERR2 ERR1 ERR0
Meaning
0
No error
0
1
Bitstuffing error
0
1
0
CRC error
01
1
EOP error (unexpected end of
packet or SE0 not followed by
J-state)
10
0
PID error (PID encoding error,
unexpected or unknown PID)
10
1
Memory over / underrun (mem-
ory controller has not an-
swered in time to a memory
data request)
11
1
Other error (wrong packet,
timeout error)
70
CTR0
DTOG
_TX
STAT _
TX1
STAT_
TX0
0
DTOG
_RX
STAT_
RX1
STAT_
RX0
STAT_TX1 STAT_TX0
Meaning
00
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
01
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
10
NAK: the endpoint is NAKed
and all transmission requests
result in a NAK handshake.
11
VALID: this endpoint is enabled
(if an address match occurs, the
USB interface handles the
transaction).
1
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