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参数资料
| 型号： | ST72F652R4T1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, TQFP-64 |
| 文件页数： | 157/160页 |
| 文件大小： | 974K |
| 代理商： | ST72F652R4T1 |
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.7.4 Functional Description
Figure 57 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (SPICR)
– A Control Status Register (SPICSR)
– A Data Register (SPIDR)
Refer to the SPICR, SPICSR and SPIDR registers
in Section 11.7.5for the bit definitions.
11.7.4.1 SS Signal in Hardware/Software Mode
The SS signal can be obtained in two modes:
– Hardware mode (through the SS pin)
– Software mode (through the SSI bit in the SPIC-
SR register)
The mode (hardware or software) is selected by
the Slave Selection Mode (SSM) bit in the SPICSR
register.
Note: In this document, wherever SS signal selec-
tion is done using the SS pin (hardware mode),
this can also be done in software mode, using the
SSM and SSI bits.
11.7.4.2 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
Procedure
1. Select the SPR[2:0] bits to define the serial
clock baud rate (see SPICR register).
2. Select the CPOL and CPHA bits to define
one of the four relationships between the
data transfer and the serial clock (see Figure
60).
Caution: In all cases, the idle state of the SCK
pin must correspond to the selected polarity.
The SCK pin must be pulled up if CPOL=1, or
pulled down if CPOL=0.
3. Connect the SS pin to a high level signal dur-
ing the complete byte transmit sequence or,
in software mode, set the SSI bit in the
SPICSR register.
4. The MSTR and SPE bits must be set (they
remain set only if the SS pin is connected to
a high level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit Sequence
The transmit sequence begins when a byte is writ-
ten in the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPIDR register is
read, the SPI peripheral returns this buffered val-
ue.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
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