收藏本站
参数资料
型号： ST72F652R4T1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封装： 14 X 14 MM, TQFP-64
文件页数： 130/160页
文件大小： 974K
代理商： ST72F652R4T1
ST7265
71/160
USB INTERFACE (Cont’d)
Bits 1:0 = STAT_RX [1:0]
Status bits, for reception
transfers.
These bits contain the information about the end-
point status, as listed below:
Table 19. Reception Status Encoding
These bits are written by software. Hardware sets
the STAT_RX and STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint, so the software has the time to ex-
amine the received data before acknowledging a
new transaction.
Notes:
If a SETUP is received while the status is other
than DISABLED, it is acknowledged and the two
directional status bits are set to NAK by hardware.
When a STALL is answered by the USB device,
the two directional status bits are set to STALL by
hardware.
ENDPOINT
1
RECEPTION
REGISTER
(EP1RXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 1 re-
ception. It is also reset by a USB reset, either re-
ceived from the USB or forced through the FRES
bit in the CTLR register.
Bits 7:4 Reserved, forced by hardware to 0.
Bit 3 = CTR_RX
Correct Reception Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after the corresponding interrupt has
been serviced.
Bit 2 = DTOG_RX
Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
The receiver toggles DTOG_RX only if it receives
a correct data packet and the packet’s data PID
matches the receiver sequence bit.
Bits 1:0 = STAT_RX [1:0]
Status bits, for reception
transfers.
These bits contain the information about the end-
point status, as listed below:
Table 20. Reception Status Encoding:
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
STAT_RX1 STAT_RX0
Meaning
00
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
01
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
10
NAK: the endpoint is NAKed
and all reception requests re-
sult in a NAK handshake.
11
VALID: this endpoint is ena-
bled (if an address match oc-
curs, the USB interface
handles the transaction).
70
000
0
CTR_R
X
DTOG
_RX
STAT_
RX1
STAT_
RX0
STAT_RX1 STAT_RX0
Meaning
00
DISABLED: reception trans-
fers cannot be executed.
01
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
10
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
11
VALID: this endpoint is ena-
bled for reception.
1
相关PDF资料
PDF描述
ST733C04LHK1L 1900 A, 400 V, SCR, TO-200AC
ST733C04LHK3 1900 A, 400 V, SCR, TO-200AC
ST7PLITE09Y0U6TR 8-BIT, MROM, 8 MHz, MICROCONTROLLER, QCC20
STARX032XXEEXF120.0 INTERVAL-DELAY RELAY, DPDT, MOMENTARY, 24VDC (COIL), 3000mW (COIL), 10A (CONTACT), 28VDC (CONTACT), 120s, SOCKET MOUNT
STARX032XXEEXF4.000 INTERVAL-DELAY RELAY, DPDT, MOMENTARY, 24VDC (COIL), 3000mW (COIL), 10A (CONTACT), 28VDC (CONTACT), 4s, SOCKET MOUNT
相关代理商/技术参数
参数描述
ST72P262M6/OZXTR 制造商:STMicroelectronics 功能描述:ST72P262M6/OZXTR
ST72P324TA/OBZTR 制造商:STMicroelectronics 功能描述:
ST72P324TA/OHXTR 制造商:STMicroelectronics 功能描述:
ST72P4T128M-A05AU 制造商:STEC Inc 功能描述:1GB,ECC,REG,DDR2-400,UNLEAD - Bulk
ST72T101G1B6 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*