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参数资料
| 型号： | ST72F652R4T1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, TQFP-64 |
| 文件页数： | 159/160页 |
| 文件大小： | 974K |
| 代理商： | ST72F652R4T1 |
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.7.4.4 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Caution: In all cases, the idle state of the SCK pin
must correspond to the selected polarity. The SCK
pin must be pulled up if CPOL=1, or pulled down if
CPOL=0.
Figure 60, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 59).
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the second clock transition.
This pin must be toggled high and low between
each byte transmitted (see Figure 59).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its SPIDR register and does not allow it
to be altered. Therefore the SS pin must be high to
write a new data byte in the SPIDR without pro-
ducing a write collision.
Note: The SPI must be disabled by resetting the
SPE bit if the CPOL bit is changed at the commu-
nication byte boundaries.
11.7.4.5 Output Disable
In order to free the I/O pin so it can be used for oth-
er purposes, it is possible to disable the SPI output
function by setting the SOD bit in the SPICSR reg-
ister.
Figure 59. CPHA / SS Timing Diagram
MOSI/MISO
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
Byte 1
Byte 2
Byte 3
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