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参数资料
型号： ST72F652R4T1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封装： 14 X 14 MM, TQFP-64
文件页数： 96/160页
文件大小： 974K
代理商： ST72F652R4T1
ST7265
40/160
7 INTERRUPTS
7.1 INTRODUCTION
The ST7 enhanced interrupt management pro-
vides the following features:
s
Hardware interrupts
s
Software interrupt (TRAP)
s
Nested or concurrent interrupt management
with
flexible
interrupt
priority
and
level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: TLI, RESET, TRAP
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 7). The process-
ing flow is shown in Figure 27
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 7. Interrupt Software Priority Levels
Figure 27. Interrupt Processing Flowchart
Interrupt software priority
Level
I1
I0
Level 0 (main)
Low
High
10
Level 1
0
1
Level 2
0
Level 3 (= interrupt disable)
1
“IRET”
RESTOR E PC, X, A, CC
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRU PT SW REG.
FETCH NEXT
RESE T
TLI
PENDIN G
INSTRUC TION
I1:0
FROM STAC K
LOAD PC FROM INTERRUPT VECTOR
Y
N
Y
N
Y
N
Interrupt has the same or a
lower software priority
THE INTER RUPT
STAYS PENDING
than current one
Interrupt
has
a
higher
software
priority
than
current
one
EXECUTE
INSTRUCTION
INTERRUPT
1
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