参数资料
型号: STE10/100E
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封装: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128
文件页数: 11/66页
文件大小: 396K
代理商: STE10/100E
19/66
STE10/100A
7
RDU
Receive Descriptor Unavailable
1: when the next receive descriptor can not be obtained by the
STE10/100A. The receive process is suspended in this
situation. To restart the receive process, the ownership bit of
the next receive descriptor should be set to STE10/100A and a
receive poll demand command should be issued (if the receive
poll demand is not issued, the receive process will resume
when a new recognized frame is received).
0
RO/LH*
6
RCI
Receive Completed Interrupt
1: when a frame reception is completed.
0
RO/LH*
5
TUF
Transmit Under-Flow
1: when an under-flow condition occurs in the transmit FIFO
during transmitting. The transmit process will enter the
suspended state and report the under-flow error on bit 1 of
TDES0.
0
RO/LH*
4
---
Reserved
3
TJT
Transmit Jabber Timer Time-out
1: when the transmit jabber timer expires. The transmit
processor will enter the stop state and TO (bit 14 of TDES0,
transmit jabber time-out flag) will be asserted.
0
RO/LH*
2
TDU
Transmit Descriptor Unavailable
1: when the next transmit descriptor can not be obtained by
the STE10/100A. The transmission process is suspended in
this situation. To restart the transmission process, the
ownership bit of the next transmit descriptor should be set to
STE10/100A and, if the transmit automatic polling is not
enabled, a transmit poll demand command should then be
issued.
0
RO/LH*
1
TPS
Transmit Process Stopped.
1: while transmit state = stop
0
RO/LH*
0
TCI
Transmit Completed Interrupt.
1: set when a frame transmission completes with IC (bit 31 of
TDES1) asserted in the first transmit descriptor of the frame.
0
RO/LH*
LH = High Latching and cleared by writing 1.
CSR6(offset = 30h), NAR - Network access register
31~22
---
reserved
21
SF
Store and forward for transmit
0: disable
1: enable, ignore the transmit threshold setting
0
R/W*
20
---
reserved
19
SQE
SQE Disable
0: enable SQE function for 10BASE-T operation. The STE10/
100A provides SQE test function for 10BASE-T half duplex
operation.
1: disable SQE function.
1
R/W*
18~16
-----
reserved
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type
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