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参数资料
| 型号： | STE10/100E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封装： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件页数： | 18/66页 |
| 文件大小： | 396K |
| 代理商： | STE10/100E |
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STE10/100A
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type
CSR15(offset = 78h), WTMR - Watchdog timer
31~6
---
Reserved
5
RWR
Receive Watchdog Release. The time (in bit-times) from
sensing dropped carrier to releasing watchdog timer.
0: 24 bit-times
1: 48 bit-times
0
R/W
4
RWD
Receive Watchdog Disable
0: If the received packet‘s length exceeds 2560 bytes, the
watchdog timer will expire.
1: disable the receive watchdog.
0
R/W
3
---
Reserved
2
JCLK
Jabber clock
0: cut off transmission after 2.6 ms (100Mbps) or 26 ms
(10Mbps).
1: cut off transmission after 2560 byte-time.
0
R/W
1
NJ
Non-Jabber
0: if jabber expires, re-enable transmit function after 42 ms
(100Mbps) or 420ms (10Mbps).
1: immediately re-enable the transmit function after jabber
expires.
0
R/W
0
JBD
Jabber disable
1: disable transmit jabber function
0
R/W
CSR16(offset = 80h), ACSR5 - Assistant CSR5(Status register 2)
31
TEIS
Transmit Early Interrupt status
Transmit early interrupt status is set to 1 when TEIE (bit 31 of
CSR17 set) is enabled and the transmitted packet is moved
from descriptors to the TX-FIFO buffer. This bit is cleared by
writing a 1.
0
RO/LH*
30
REIS
Receive Early Interrupt Status.
Receive early interrupt status is set to 1 when REIE (CSR17
bit 30) is enabled and the received packet has filled up its first
receive descriptor. This bit is cleared by writing a 1.
0
RO/LH*
29
XIS
Transceiver (XCVR) Interrupt Status. Formed by the logical
OR of XR8 bits 6~0.
1
RO/LH*
28
TDIS
Transmit Deferred Interrupt Status.
0
RO/LH*
27
---
Reserved
26
PFR
PAUSE Frame Received Interrupt Status
1: indicates receipt of a PAUSE frame while the PAUSE
function is enabled.
0
RO/LH*
25~ 23
BET
Bus Error Type. This field is valid only when FBE (CSR5 bit 13,
fatal bus error) is set. There is no interrupt generated by this
field.
000: parity error, 001: master abort, 010: target abort
011, 1xx: reserved
000
RO
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