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参数资料
| 型号： | STE10/100E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封装： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件页数： | 16/66页 |
| 文件大小： | 396K |
| 代理商： | STE10/100E |
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23/66
STE10/100A
30
CRCT
CRC-16 Type
0: Initial contents = 0000h
1: Initial contents = FFFFh
0
R/W
29
WP1E
Wake-up Pattern One Matched Enable.
0
R/W
28
WP2E
Wake-up Pattern Two Matched Enable.
0
R/W
27
WP3E
Wake-up Pattern Three Matched Enable.
0
R/W
26
WP4E
Wake-up Pattern Four Matched Enable.
0
R/W
25
WP5E
Wake-up Pattern Five Matched Enable.
0
R/W
24-18
---
Reserved
17
LinkOFF
Link Off Detect Enable. The STE10/100A will set the LSC bit of
CSR13 after it has detected that link status has transitioned
from ON to OFF.
0
R/W
16
LinkON
Link On Detect Enable. The STE10/100A will set the LSC bit
of CSR13 after it has detected that link status has transitioned
from OFF to ON.
0
R/W
15-11
---
Reserved
10
WFRE
Wake-up Frame Received Enable. The STE10/100A will
include the “Wake-up Frame Received” event in its set of
wake-up events. If this bit is set, STE10/100A will assert
PMEST bit of PMR1 (CR49) after STE10/100A has received a
matched wake-up frame.
0
R/W
9
MPRE
Magic Packet Received Enable. The STE10/100A will include
the “Magic Packet Received” event in its set of wake-up
events. If this bit is set, STE10/100A will assert PMEST bit of
PMR1 (CR49) after STE10/100A has received a Magic packet.
Default 1 if
PM & WOL
bits of CSR
18 are both
enabled.
R/W
8
LSCE
Link Status Changed Enable. The STE10/100A will include the
“Link Status Changed” event in its set of wake-up events. If
this bit is set, STE10/100A will assert PMEST bit of PMR1
after STE10/100A has detected a link status changed event.
0
R/W
7-3
---
Reserved
2
WFR
Wake-up Frame Received,
1: Indicates STE10/100A has received a wake-up frame. It is
cleared by writing a 1 or upon power-up reset. It is not
affected by a hardware or software reset.
X
R/W1C*
1
MPR
Magic Packet Received,
1: Indicates STE10/100A has received a magic packet. It is
cleared by writing a 1 or upon power-up reset. It is not
affected by a hardware or software reset.
X
R/W1C*
0
LSC
Link Status Changed,
1: Indicates STE10/100A has detected a link status change
event. It is cleared by writing a 1 or upon power-up reset. It
is not affected by a hardware or software reset.
X
R/W1C*
R/W1C*, Read Only and Write one cleared.
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type
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