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参数资料
| 型号： | STE10/100E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封装： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件页数： | 3/66页 |
| 文件大小： | 396K |
| 代理商： | STE10/100E |
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STE10/100A
0
CIOSA
Command I/O Space Access
0: enable the I/O space access ability.
1: disable the I/O space access ability.
1
R/W
R/W: Read and Write able. RO: Read able only.
CR2(offset = 08h), CC - Class Code and Revision Number
31~24
BCC
Base Class Code. It means STE10/100A is a network
controller.
02h
RO
23~16
SC
Subclass Code. It means STE10/100A is a Fast Ethernet
Controller.
00h
RO
15~ 8
---
Reserved.
7 ~ 4
RN
Revision Number, identifies the revision number of STE10/
100A.
Ah
RO
3 ~ 0
SN
Step Number, identifies the STE10/100A steps within the
current revision.
1h
RO
RO: Read Only.
CR3(offset = 0ch), LT - Latency Timer
31~16
---
Reserved.
15~ 8
LT
Latency Timer. This value specifies the latency timer of the
STE10/100A in units of PCI bus clock cycles. Once the STE10/
100A asserts FRAME#, the latency timer starts to count. If the
latency timer expires and the STE10/100A is still asserting
FRAME#, the STE10/100A will terminate the data transaction
as soon as its GNT# is removed.
40h
R/W
7 ~ 0
CLS
Cache Line Size. This value specifies the system cache line
size in units of 32-bit double words(DW). The STE10/100A
supports cache line sizes of 8, 16, or 32 DW. CLS is used by
the STE10/100A driver to program the cache alignment bits
(bit 14 and 15 of CSR0) which are used for cache oriented PCI
commands, e.g., memory-read-line, memory-read-multiple,
and memory-write-and-invalidate.
08h
R/W
CR4(offset = 10h), IOBA - I/O Base Address
31~ 7
IOBA
I/O Base Address. This value indicate the base address of PCI
control and status register (CSR0~28), and Transceiver
registers (XR0~10)
0
R/W
6 ~ 1
---
reserved.
0
IOSI
I/O Space Indicator.
1: means that the configuration registers map into I/O space.
1RO
CR5(offset = 14h), MBA - Memory Base Address
31~ 7
MBA
Memory Base Address. This value indicate the base address
of PCI control and status register(CSR0~28), and Transceiver
registers(XR0~10)
0
R/W
6 ~ 1
---
reserved.
Table 4. Configuration Registers Descriptions
Bit #
Name
Descriptions
Default Val
RW Type
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相关代理商/技术参数 |
参数描述 |
|---|---|
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