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参数资料
| 型号： | STE10/100E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封装： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件页数： | 4/66页 |
| 文件大小： | 396K |
| 代理商： | STE10/100E |
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STE10/100A
12/66
0
IOSI
Memory Space Indicator.
1: means that the configuration registers map into I/O space.
0RO
CR11(offset = 2ch), SID - Subsystem ID.
31~16
SID
Subsystem ID. This value is loaded from EEPROM as a result
of power-on or hardware reset.
From
EEPROM
RO
15~ 0
SVID
Subsystem Vendor ID. This value is loaded from EEPROM as
a result power-on or hardware reset.
From
EEPROM
RO
CR12(offset = 30h), BRBA - Boot ROM Base Address. This register should be initialized before accessing the
boot ROM space.
31~10
BRBA
Boot ROM Base Address. This value indicates the address
mapping of the boot ROM field as well as defining the boot
ROM size. The values of bit 16~10 are set to 0 indicating that
the STE10/100A supports up to 128kB of boot ROM.
X: b31~17
0: b16~10
R/W
RO
9 ~ 1
---
reserved
RO R/W R/
W
0
BRE
Boot ROM Enable. The STE10/100A will only enable its boot
ROM access if both the memory space access bit (bit 1 of
CR1) and this bit are set to 1.
1: enable Boot ROM. (if bit 1 of CR1 is also set)
0
R/W
CR13(offset = 34h), CP - Capabilities Pointer.
31~8
---
reserved
7~0
CP
Capabilities Pointer.
C0H
RO
CR15(offset = 3ch), CI - Configuration Interrupt
31~24
ML
Max_Lat register. This value indicates how often the STE10/
100A needs to access to the PCI bus in units of 250ns. This
value is loaded from serial EEPROM as a result of power-on
or hardware reset.
From
EEPROM
RO
23~16
MG
Min_Gnt register. This value indicates how long the STE10/
100A needs to retain the PCI bus ownership whenever it
initiates a transaction, in units of 250ns. This value is loaded
from serial EEPROM as a result power-on or hardware reset.
From
EEPROM
RO
15~ 8
IP
Interrupt Pin. This value indicates one of four interrupt request
pins to which the STE10/100A is connected.
01h: means the STE10/100A always connects to INTA#
01h
RO
7 ~ 0
IL
Interrupt Line. This value indicates the system interrupt
request lines to which the INTA# of STE10/100A is routed. The
BIOS will fill this field when it initializes and configures the
system. The STE10/100A driver can use this value to
determine priority and vector information.
0
R/W
CR16(offset = 40h), DS - Driver Space for special purpose.
31~16
---
reserved
Table 4. Configuration Registers Descriptions
Bit #
Name
Descriptions
Default Val
RW Type
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