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参数资料
| 型号： | STE10/100E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封装： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件页数： | 19/66页 |
| 文件大小： | 396K |
| 代理商： | STE10/100E |
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STE10/100A
26/66
22~ 20
TS
Transmit State. Reports the current transmission state only, no
interrupt will be generated.
000: stop
001: read descriptor
010: transmitting
011: FIFO fill, read the data from memory and put into FIFO
100: reserved
101: reserved
110: suspended, unavailable transmit descriptor or FIFO
overflow
111: write descriptor
000
RO
19~17
RS
Receive State. Reports current receive state only, no interrupt
will be generated.
000: stop
001: read descriptor
010: check this packet and pre-fetch next descriptor
011: wait for receiving data
100: suspended
101: write descriptor
110: flush the current FIFO
111: FIFO drain, move data from receiving FIFO into memory
000
RO
16
ANISS
Added normal interrupt status summary.
1: whenever any of the added normal interrupts occur.
0
RO/LH*
15
AAISS
Added Abnormal Interrupt Status Summary.
1: whenever any of the added abnormal interrupts occur.
1
RO/LH*
14~0
These bits are the same as the status register of CSR5, and
are accessible through either CSR5 or CSR16.
LH* = High Latching and cleared by writing 1.
CSR17(offset = 84h), ACSR7- Assistant CSR7(Interrupt enable register 2)
31
TEIE
Transmit Early Interrupt Enable
0
R/W
30
REIE
Receive Early Interrupt Enable
0
R/W
29
XIE
Transceiver (XCVR) Interrupt Enable
0
R/W
28
TDIE
Transmit Deferred Interrupt Enable
0
R/W
27
---
Reserved
26
PFRIE
PAUSE Frame Received Interrupt Enable
0
R/W
25~17
---
Reserved
16
ANISE
Added Normal Interrupt Summary Enable.
1: adds the interrupts of bits 30 and 31 of ACSR7 (CSR17) to
the normal interrupt summary (bit 16 of CSR5).
0
R/W
15
AAIE
Added Abnormal Interrupt Summary Enable.
1: adds the interrupt of bits 27, 28, and 29 of ACSR7 (CSR17)
to the abnormal interrupt summary (bit 16 of CSR5).
0
R/W
14~0
These bits are the same as the interrupt enable register of
CSR7, and are accessible through either CSR7 or CSR16.
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type
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