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| 型号： | STPCE1EEBC |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 58/87页 |
| 文件大小： | 1426K |
| 代理商： | STPCE1EEBC |
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DESIGN GUIDELINES
Release 1.3 - January 29, 2002
61/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
6.3. ARCHITECTURE RECOMMENDATIONS
This
section
describes
the
recommend
implementations for the STPC interfaces. For
more
details,
download
the
Reference
Schematics from the STPC web site.
6.3.1. POWER DECOUPLING
An appropriate decoupling of the various STPC
power pins is mandatory for optimum behaviour.
When insufficient, the integrity of the signals is
deteriorated, the stability of the system is reduced
and EMC is increased.
6.3.1.1. PLL decoupling
This is the most important as the STPC clocks are
generated from a single 14MHz stage using
multiple PLLs which are highly sensitive analog
cells. The frequencies to filter are the 25-50 KHz
range which correspond to the internal loop
bandwidth of the PLL and the 10 to 100 MHz
frequency of the output. PLL power pins can be
tied together to simplify the board layout.
6.3.1.2. Decoupling of 3.3V and Vcore
A power plane for each of these supplies with one
decoupling capacitance for each power pin is the
minimum. The use of multiple capacitances with
values in decade is the best (for example: 10pF,
1nF, 100nF, 10uF), the smallest value, the closest
to the power pin. Connecting the various digital
power planes through capacitances will reduce
furthermore the overall impedance and electrical
noise.
6.3.2. 14MHZ OSCILLATOR STAGE
The 14.31818 MHz oscillator stage can be
implemented
using
a
quartz,
which
is
the
preferred and cheaper solution, or using an
external 3.3V oscillator.
The crystal must be used in its series-cut
fundamental mode and not in overtone mode. It
must have an Equivalent Series Resistance (ESR,
sometimes referred to as Rm) of less than 50
Ohms (typically 8 Ohms) and a shunt capacitance
(Co) of less than 7 pF. The balance capacitors of
16 pF must be added, one connected to each pin,
as described in Figure 6-3.
In the event of an external oscillator providing the
master clock signal to the STPC Atlas device, the
LVTTL signal should be connected to XTALI, as
described in Figure 6-3.
As this clock is the reference for all the other on-
chip
generated
clocks,
it
is
strongly
recommended to shield this stage, including
the 2 wires going to the STPC balls, in order to
reduce the jitter to the minimum and reach the
optimum system stability.
Figure 6-2. PLL decoupling
VDD_PLL
VSS_PLL
PWR
100nF 47uF
GND
Connections must be as short as possible
Figure 6-3. 14.31818 MHz stage
15pF
XTALO
XTALI
XTALO
XTALI
3.3V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| STPCE1EEBI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip |
| STPCE1HDBC | 制造商:STMicroelectronics 功能描述:X86 GENERAL PURPOSE CONTROLLER - Bulk |
| STPCE1HDBI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip |
| STPCE1HDC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| STPCE1HEBC | 功能描述:微处理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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