参数资料
型号: TLC320AC01CPMR
厂商: TEXAS INSTRUMENTS INC
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP64
封装: PLASTIC, QFP-64
文件页数: 41/93页
文件大小: 601K
代理商: TLC320AC01CPMR
3–9
3.7
Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode
3.7.1
Recommended Input Timing Requirements for Slave Mode, VDD = 5 V
MIN
NOM
MAX
UNIT
tr(MCLK)
Master clock rise time
5
ns
tf(MCLK)
Master clock fall time
5
ns
Master clock duty cycle
40%
60%
tw(RESET)
RESET pulse duration
1 MCLK
tsu(DIN)
DIN setup time before SCLK low (see Figure 4–3)
20
ns
th(DIN)
DIN hold time after SCLK high (see Figure 4–3)
20
ns
tsu(FL-CH)
Setup time from FS low to SCLK high
±SCLK/4
ns
3.7.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, VDD = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
MIN
TYP
MAX
UNIT
tc(SCLK)
Shift clock cycle time (see Figure 4–3)
125
ns
tf(SCLK)
Shift clock fall time (see Figure 4–3)
18
ns
tr(SCLK)
Shift clock rise time (see Figure 4–3)
18
ns
Shift clock duty cycle
45%
55%
td(CH-FDL)
Delay time from SCLK high to FSD low (see Figure 4–6)
50
ns
td(CH-FDH)
Delay time from SCLK high to FSD high
40
ns
td(FL-FDL)
Delay time from FS low to FSD low (slave to slave)
(see Figure 4–5)
40
ns
td(CH-DOUT)
Delay time from SCLK high to DOUT valid
(see Figures 4–3 and 4–7)
40
ns
td(CH-DOUTZ)
Delay time from SCLK
↑ to DOUT in high-impedance state
(see Figure 4–8)
20
ns
td(ML-EL)
Delay time from MCLK low to EOC low (see Figure 4–9)
40
ns
td(ML-EH)
Delay time from MCLK low to EOC high (see Figure 4–9)
40
ns
tf(EL)
EOC fall time (see Figure 4–9)
13
ns
tr(EH)
EOC rise time (see Figure 4–9)
13
ns
td(MH-CH)
Delay time from MCLK high to SCLK high
50
ns
td(MH-CL)
Delay time from MCLK high to SCLK low
50
ns
All typical values are at VDD = 5 V and TA = 25°C.
NOTE 23: All timing specifications are valid with CL = 20 pF.
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