参数资料
型号: TLC320AC01CPMR
厂商: TEXAS INSTRUMENTS INC
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP64
封装: PLASTIC, QFP-64
文件页数: 44/93页
文件大小: 601K
代理商: TLC320AC01CPMR
4–2
D15
D14
D13
D12
D11
D2
D1
D0
tf(SCLK)
0.8 V
SCLK
FS
tr(SCLK)
td(CH-FH)
td(CH-FL)
0.8 V
2 V
td(CH-DOUT)
D15
D14
D13
D12
D11
D2
D1
D0
tsu(DIN)
th(DIN)
DOUT
DIN
2 V
The time between falling edges of two primary FS signals is the conversion period.
The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
Figure 4 – 2. AIC Stand-Alone and Master-Mode Timing
D15
D14
D13
D12
D11
D2
D1
D0
2 V
tf(SCLK)
0.8 V
SCLK
FS
tr(SCLK)
tc(SCLK)
§
2 V
td(CH-DOUT)
D15
D14
D13
D12
D11
D2
D1
D0
tsu(DIN)
th(DIN)
DOUT
DIN
The time between falling edges of two primary FS signals is the conversion period.
The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
§ The high-to-low transition of FS must must occur within
±1/4 of a shift-clock period around the 2-V level of the shift clock
for the codec mode.
Figure 4 – 3. AIC Slave and Codec Emulation Mode
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