TOSHIBA
TMPR3904F Rev. 2.0
97
9.4.3
32/16-bit Static Bus Sizing
The bus width 32/16 bits of the ROM that is connected to the ROM Channel 0 is designated by
an external input pin (BOOT16). The value of this input pin will be taken in to the 16BUS0 of
the channel control register 0 at the time of reset. The bus width of the ROM channel 1 is set up
by the program.
9.4.4
16-bit Bus Access
Word/triple-byte access with 16-bit width ROM
If the 16BUSn of the ROM channel control register is 1 when a word/triple-byte access is
requested, the ROMC executes two bus cycles with the timing set up in the register.
Half-word/byte access with 16-bit width ROM
If the 16BUSn of the ROM channel control register is 1 when a 16-bit data access is requested,
the ROMC executes one bus cycle with the timing set up in the register.
9.4.5
Access by External Bus Master
The ROMC drives address(es) with the built-in address counter at the times of page mode access
(page mode mask ROM) and interleave access. When the external bus master conducts a
memory access using the ROMC of the TX3904, an address bus conflict may occur. The
external bus master must stop the drive of the address bus and the BE* at a rising of the
BSTART*. When having received a memory access request from the external bus master, the
ROMC automatically inserts a wait cycle to avoid driving the address, CE*, OE*, and SWE* at
the S1 state. The number of the automatically inserted wait cycles is 1 SYSCLK. AT a single
access, the address output by the external bus master is given to the memory. Therefore, at this
time, please do not stop the address drive.
In the half speed bus mode, please adjust the wait such that the number of the cycles (GCLK) of
the internal system clock should be an even number.
9.4.6
Page mode support
In the case of a page mode mask ROM, the ROM controller conducts page mode access when
the bus master executes the burst mode access. The bus master issues a burst starting address
for the first word, then the ROM controller generates the successive address for the second word
and after. The ROM controller increments address like as 0-4-8-C-10-... if the lower four-bit of
burst starting address is 0x0. On the other hand, it decrements address like as C-8-4-0-... if the
starting address is 0xC.