Users Manual
28
The halt bit must be set to 1 with an example flow shown below in order
to make the TX3904 halt mode. An exception must be caused when the
TX3904 is recovered form halt mode. An interrupt must not be masked.
address
0x_
0x_c
0x_0
0x_4
0x_8
0x_c label:
instruction
mfc0 r25, r3
sync
ori r25, r25, 0x100
j label
mtc0 r25, r3
comment
# read Config register
#
# set HALT bit
#
# write Config register
A store instruction which sets a halt bit in the configuration register of the TX39
processor core must be placed on an address whose low four bit is 0x8. If not, the
TMPR3904F may not return to the normal mode correctly.
6.2.3
Doze mode
The doze mode is a mode to lower power consumption by partially
halting the TX39 Processor Core
’
s operations. The difference from the
halt mode is that bus release requests from outside can be accepted
because the doze mode halts some of the clocks inside the Processor
Core. The peripheral blocks continue normal operations.
By setting the doze bit of the Config register of the TX39 Processor Core,
it shifts to the doze mode.
When having entered into the doze mode, the TX39 mega cell core halts
operations while maintaining the pipeline status. The write buffer does
not halt. Therefore, if there are remaining data in the write buffer in the
doze mode, the write operation continues until the buffer becomes
empty. The SYSCLK does not halt, either.
The doze mode is recovered from when the doze bit is cleared to 0 by
asserting the interrupts by on-chip peripherals (internal interrupt),
INT[7:0], NMI*, or RESET* signal. The value in the IntMask field of the
status register is not affected by the recovery from the doze mode. If
recovered by the RESET* signal, NMI* signal, or non-masked (internal
interrupt) and INT[7:0] signal, the corresponding exception handler is
executed. If recovered by the masked (internal interrupt) and INT[7:0]
signal, execution resumes from the instruction that follows the
instruction that was being executed when shifted to the doze mode.
6.2.4
RF (Reduced Frequency) mode
The frequency of the clock is controlled by operating the clock generator
by setting up the RF field of the Config register of the TX39 Processor
Core. When an instruction to change the RF field is executed while the
bus ownership is being released, the clock
’
s frequency is changed
without waiting for the bus ownership to be returned. Also when the RF