TOSHIBA
TMPR3904F Rev. 2.0
41
7.2
Bus Error
7.2.1
BUSERR* signal
The TX3904 employs the BUSERR* input signal. The peripheral circuits can
report that problems occurred during a bus operation by asserting a BUSERR*
signal. The following operation occurs with respect to the BUSERR* signal.
*
During read operation of the TX 39 processor core
The TX3904 immediately suspends the read operation. The TX39
processor core generates a bus error exception.
*
During write operation of the TX 39 processor core
The TX3904 immediately suspends the write operation. The TX39
processor core generates a nonmaskable interrupt exception. Also, “1” is set to
the BEOW bit of the CConR register.
*
During bus operation of the TX 3904 on-chip DMA controller
The DMA controller immediately suspends transfer operation, then
abnormally ends the channel operation. The DMA controller generates an
interrupt if abnormal end interrupts are not prohibited.
7.2.2
Absence register access
Access to an address which does not actually exist in a register is processed as
a bus error in each module register area inside the TX3904. Also, a bus error
is generated when the external bus master attempts to access the inside of the
TX3904 (0xFFxx_xxxx).
A bus error exception is generated during read operation by the TX39
processor core. A nonmaskable interrupt exception is generated during a write
operation by the TX39 processor core.
7.2.3
Time-out error
If there is no response within 256 SYSCLK after the bus operation started, the
R3904 can generate a bus error exception as a time-out error. To use the
time-out error, set 1 to the TOE bit of the CConR. A time-out error occurs also
in a bus operation by the external bus master.
A time-out error occurs when the ACK* signal (external or internal) is not
asserted even after 256 SYSCLK has passed from the SYSCLK at which the
BSTART* was asserted. Also, in the burst read operation, a time-out error
occurs when the number of SYSCLK between the ACK* signals reaches 256.
The following operation occurs with respect to the time out error.
*
During read operation of the TX 39 processor core
The TX39 processor core generates a bus error exception.
*
During write operation of the TX 39 processor core
The TX39 processor core generates a non-maskable interrupt
exception. Also, “1” is set to the BEOW bit of the CConR register.