TOSHIBA
TMPR3904F Rev. 2.0
122
26
10.3.2 Channel control register (CCRn)
TrSiz
DIO
DAC
SAC
SIO
RelEn
SReq
Lev
PosE
ExR
SAM
DPS
17
18
20
19
24
21
22
23
25
30
31
16
15
0
: Type
: Initial
Value
: Type
: Initial
Value
Cont
Big
DOEn
DIEn
0
CIEn
AbIEn
NIEn
Stop
0
Str
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
1
1
1
0
0
0
0
0
0
0
0
00
00
00
00
1
2
14
13
12
10
11
9
8
7
6
5
4
3
R/W
0
Bit
31
Mnemonic
Str
Name of Field
Channel start
Description
Start
Starts the channel operation. By setting up this bit to 1,
the channel becomes the wait status and starts a data
transfer in response to a transfer request.
“1” is only valid to write in to the Str bit and the writing-in
of “0” is ignored. When read out, it is always “0.”
1: Starts the channel operation.
Stop
Completes the channel operation to change the channel to
the halt status. The SARn and the DARn maintain the
address following the address with which the last transfer
was made. The BCRn maintains the rest of the number of
transfer bytes.
When the channel is not in the wait status, writing-ins are
ignored.
“1” is only valid to write in to the Stop bit and the writing-
in of “0” is ignored. When read out, it is always “0.” Do
not set this bit “0” when the channel is not in the wait
satate.
When the Str bit and the Stop bit are simultaneously set up
to 1, the channel becomes the wait status.
1: Competes the channel operation.
Normal Completion Interrupt Enable
1: Grants a normal completion interrupt
0: Inhibits a normal completion interrupt
24
Stop
Channel stop
23
NIEn
Normal
completion
interrupt
enable
Abnormal
completion
interrupt
enable
22
AbEn
Abnormal Completion Interrupt Enable
1: Grants an abnormal completion interrupt
0: Inhibits an abnormal completion interrupt
Fig. 10-4 Channel Control Registers (CCRn) (1/4)