TOSHIBA
TMPR3904F Rev. 2.0
149
26
Abnormal completion
The following cases are the abnormal completion of the DMAC.
Completion by configuration error
The configuration error is a mistake in the set-up of the DMA transfer. A configuration error
occurs before a data transfer operation is started so that the values of SARn, DARn, and BCRn
are the same as the set-up time. When a channel completes abnormally by a configuration error,
the AbC bit of the CSRn is set to 1 and, at the same time, the Conf bit is set to 1. The following
are the causes of the configuration error:
- To have set up I/O devices for both the source device and the destination device.
- To have set up memories for both the source device and the destination device in the single
mode.
- To have set up the continue mode when it is the dual address mode.
- To have set 1 to the Str bit of the CCRn when the value of NC bit or the AbC bit of the CSRn
is 1.
- To have set up the BCRn with a value that is indivisible by the data transfer unit.
- To have set up the SARn and the DARn with a value that is indivisible by the data transfer
unit.
- To have set up the data transfer unit larger than the device port size.
- To have set 1 to the Str bit of the CCRn when the BCRn value is 0.
Completion by bus error
By an abnormal completion by a bus error, the AbC bit of the CSRn is set to 1 and,
at the same time, 1 is set to the BES bit or the BED bit
- A bus error is informed during the data transfer.
If the BUSERR* is low at a rising of the clock that acknowledges the acknowledge signal, the
DMAC terminates the data transfer.