9.5.8 32-bit bus page mode burst read operation (Page mode MROM) ...........................................106
9.5.9 16-bit bus word normal mode burst read operation (ROM/SRAM)........................................107
9.5.10 16-bit bus page mode burst read (word) operation (Page mode MROM) .............................108
9.5.11 32-bit bus normal mode burst write (SRAM)........................................................................109
9.5.12 16-bit bus normal mode burst write (word) (SRAM; WE control write)...............................110
9.5.13 16-bit bus normal mode burst write (half word) (SRAM; WE control).................................111
9.6
Examples of MROM/EPROM Usage..............................................................................................112
9.7
Examples of SRAM Usage..............................................................................................................114
10 DMA CONTROLLER (DMAC)................................................................................................................116
10.1
Features............................................................................................................................................116
10.2
Configuration...................................................................................................................................117
10.2.1TX3904 internal connection .............................................................................................................117
10.2.2DMAC internal blocks......................................................................................................................118
10.2.3 Priority between modules.................................................................................................................118
10.3
Registers...........................................................................................................................................120
10.3.1 DMA control register (DCR).................................................................................................121
10.3.2 Channel control register (CCRn)...........................................................................................122
10.3.3 Channel status register (CSRn)..............................................................................................126
10.3.4 Source address register (SARn).............................................................................................129
10.3.5 Destination address register (DARn).....................................................................................130
10.3.6 Byte count register (BCR0n) .................................................................................................131
10.3.7 Next byte count register (NCR0/1)........................................................................................132
10.3.8 Data holding register (DHR) .................................................................................................133
10.4
Functions..........................................................................................................................................134
10.4.1 Overview................................................................................................................................134
10.4.2 Transfer requests....................................................................................................................138
10.4.3 Address modes.......................................................................................................................142
10.4.4 Burst transfer .........................................................................................................................147
10.4.5 Continue mode.......................................................................................................................147
10.4.6 Channel operation..................................................................................................................148
10.4.7 Endian switch function ..........................................................................................................152
10.5
Operations........................................................................................................................................153
10.5.1 Dual address mode.................................................................................................................153
10.5.2 Single address mode..............................................................................................................156
10.5.3 Input of DONE* signal..........................................................................................................159
10.5.4 Output of DONE* signal.......................................................................................................160
10.5.5 Note for DRAM refresh during DMA...................................................................................160