TOSHIBA
TMPR3904F Rev. 2.0
210
13.4
Operations
This section describes the case of Timer 2 because the operations are the same for Timers 2, 1
and 0. If there are differences on different channels, they shall be explained individually.
13.4.1
Interval timer mode
It is set up to the interval timer mode by the timer mode (TMODE)=00 of the timer control
register (TCRn; n=0,1,2). The counter clock select (CCS) of the TCRn designates to use either
the internal system clock or the external input clock. (Timer 0 can use only the internal system
clock.)
When having selected the internal system clock, the clock that results from dividing the internal
system clock can be regarded as the input of the 24-bit counter. The set up of the divider is
conducted by the counter clock divide (CCD) of the divider register when the counter clock
divide enable (CCDE) of the TCRn is 1. From 2
1
to 2
8
dividing of the internal system clock can
be set up. When having selected the external input clock, the clock edge that operates to count
can be selected in the external clock edge select (ECES) of the TCRn.
When the timer count enable (TCE) of the TCRn is set to 1, the 24-bit counter starts counting.
When the count value matches the value of the compare register A (CPRA), a flag (“1”) is
hoisted to the timer interval interrupt status (TIIS) of the status register (TISRn; n=2,1,0). The
interrupt control logic asserts the timer interrupt request signal TMINTREQ* when 1 is set to
the timer interval interrupt enable (TIIE) of the interval timer mode register (ITMRn; n=2,1,0).
When 0 is set to the TIIE, the TMINTREQ* shall not be asserted. When “0” is written into the
TIIS of the timer interrupt status register, the TIIS shall be cleared and the TMINTREQ* shall
be deasserted. The writing-in of “1” to the TIIS is ignored.
When the timer zero clear enable (TZCE) of the ITMRn is set to 1, the 24-bit counter is cleared
to 0 when the count value matches the value of the CPRA. When the TZCE is 0, the count
operation is halted when the count value matches the value of the CPRA. The interrupt request
occurrences are summarized in the Table 0-4 below.
Table 13-4 Interrupt Control by TIIE and TZCE
TIIE
0
1
TZCE
*
0
Interrupt operation when the counter has reached the set-up value.
Interrupt does not occur.
An interrupt occurs. If TZCE=0 when having recovered (write “0”
to the TIIS) from the interrupt, another interrupt shall not occur.
When the interrupt is recovered after TZCE=1 is set, it is the same
as the cases of TIIE=1 and TZCE=1.
An interrupt occurs.
1
1
The reading of the count value can be done by reading the timer read register (TRRn; n=2,1,0).
The value that was read from the TRRn is a copy of the count value of the 24-bit counter.
Fig. 9-14 shows the outline of the count operation and interrupt occurrences in the interval timer
mode.
Fig. 9-15 shows the operation using the external input clock.