TOSHIBA
TMPR3904F Rev. 2.0
120
26
10.3
Registers
The following diagram shows fourteen built-in 32-bit registers of the DMAC. Tables 10-1 and
10-2 show the register maps of DMAC0 and DMAC1.
Table 10-1 DMAC0 Registers
Address
Register
Symbol
DHR0
DCR0
NCR1
BCR1
DAR1
SAR1
CSR1
CCR1
NCR0
BCR0
DAR0
SAR0
CSR0
CCR0
Name of Register
0xFFFF-A08C
0xFFFF-A080
0xFFFF-A034
0xFFFF-A030
0xFFFF-A02C
0xFFFF-A028
0xFFFF-A024
0xFFFF-A020
0xFFFF-A014
0xFFFF-A010
0xFFFF-A00C
0xFFFF-A008
0xFFFF-A004
0xFFFF-A000
Data holding register (DMAC0)
DMA control register (DMAC0)
Next byte count register (Ch.1)
Byte count register (Ch.1)
Destination address register (Ch.1)
Source address register (Ch.1)
Channel status register (Ch.1)
Channel control register (Ch.1)
Next byte count register (Ch.0)
Byte count register (Ch.0)
Destination address register (Ch.0)
Source address register (Ch.0)
Channel status register (Ch.0)
Channel control register (Ch.0)
Table 10-2 DMAC1 Registers
Address
Register
Symbol
DHR1
DCR1
NCR3
BCR3
DAR3
SAR3
CSR3
CCR3
NCR2
BCR2
DAR2
SAR2
CSR2
CCR2
Name of Register
0xFFFF-B08C
0xFFFF-B080
0xFFFF-B034
0xFFFF-B030
0xFFFF-B02C
0xFFFF-B028
0xFFFF-B024
0xFFFF-B020
0xFFFF-B014
0xFFFF-B010
0xFFFF-B00C
0xFFFF-B008
0xFFFF-B004
0xFFFF-B000
Data holding register (DMAC1)
DMA control register (DMAC1)
Next byte count register (Ch.3)
Byte count register (Ch.3)
Destination address register (Ch.3)
Source address register (Ch.3)
Channel status register (Ch.3)
Channel control register (Ch.3)
Next byte count register (Ch.2)
Byte count register (Ch.2)
Destination address register (Ch.2)
Source address register (Ch.2)
Channel status register (Ch.2)
Channel control register (Ch.2)