TOSHIBA
TMPR3904F Rev. 2.0
147
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10.4.4 Burst transfer
In the single address mode, the burst transfer is supported for the fast data transfer. It is
available for the data transfer between 32-bit width memory and 32-bit width I/O device. Set 0x
(32 bits) to the TrSiz and 11 (8 bits) to the DPS in the single address mode in order to use burst
transfer.
In the burst transfer, four words data transfer are occurred for one data transfer request. The
lower four bits of a start address of a burst transfer is restricted as follows.
Start address
0
C
others
address change
0
→
4
→
8
→
C
C
→
8
→
4
→
0
inhibited
10.4.5 Continue mode
In the single address mode, the continue mode can be used for operation. The set-up of the
continue mode is designated in the Cont bit of the CCRn.
In the continue mode, immediately after a data transfer has completed normally, the next data
transfer starts. The DARn value is loaded to the SARn when a memory is the source device;
and the SARn value is loaded to the DARn when a memory is the destination device; and a new
data transfer start address is implemented. Also, the NCRn value is loaded to the BCRn to
change to the number of a new transfer bytes.
In the continue mode, the NCC bit of the CSRn is set to 1 when a data transfer completes
normally. A continue interrupt occurs when the CIEn bit of the CCRn is 1. Then, the next
transfer address and the number of bytes are set up, and automatically the Cont bit is cleared to
0. After this series of operations, when the bus ownership has returned to the TX39 Processor
Core, set up the next transfer address and the number of the next transfer bytes and set the Cont
bit to 1 as a process to cope with the continue interrupt. If the Cont bit is not set to 1, the
channel operation finishes when the data transfer has completed.
The channel operation in the continue mode can be finished also by setting the Stop bit to 1.