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参数资料
| 型号： | W949D2CBJX6E |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90 |
| 文件页数： | 28/60页 |
| 文件大小： | 1160K |
| 代理商： | W949D2CBJX6E |
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W949D6CB / W949D2CB
512Mb Mobile LPDDR
Publication Release Date: Jun, 14, 2011
- 34 -
Revision A01-006
7.6.1 Write Command
= Don't Care
(High)
CK
CKE
CS
RAS
CAS
WE
A0-An
CA
AP
BA=BANK Address
CA=Coulmn Address
AP=Auto Precharge
BA
BA0,BA1
A10
Enable AP
Disable AP
7.6.2 Basic Write Timing Parameters
Basic Write timing parameters for DQs are shown in figure below; they apply to all Write operations.
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the
memory; if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be
executed to that byte / column location.
DI
n
DI
n
tCK
tCH
tCL
tDSH
tDQSH
tDQSS
tWPRES
tWPRE
tDS
tDH
tDQSL
tWPST
CK
DQS
DQ, DM
Case 1:
tDQSS =
min
Case 2:
tDQSS =
max
tDH
tDS
tWPRES
tWPRE
tDQSH
tDQSS
tDSS
tDQSL
tDSS
tWPST
= Don't Care
1) DI n=Data In for column n
2) 3 subsequent elements of Data In are applied in the programmed order following DI n.
3) tDQSS: each rising edge of DQS must fall within the +/-25% window of the corresponding positive
clock edge.
DQ, DM
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W949D2CBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 166MHZ, 65NM |
| W949D2CBJX6G | 制造商:WINBOND 制造商全称:Winbond 功能描述:512Mb Mobile LPDDR |
| W949D2KBJX5E | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W949D2KBJX5I | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W949D2KBJX6E | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 166MHZ 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
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