参数资料
型号: W949D2CBJX6E
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: 16M X 32 DDR DRAM, 5 ns, PBGA90
封装: 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90
文件页数: 48/60页
文件大小: 1160K
代理商: W949D2CBJX6E
W949D6CB / W949D2CB
512Mb Mobile LPDDR
Publication Release Date: Jun, 14, 2011
- 52 -
Revision A01-006
PARAMETER
SYMBOL
- 5
- 6
- 75
UNIT
NOTES
MIN
MAX
MIN
MAX
MIN
MAX
period
Write preamble setup time
tWPRES
0
ns
21
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
22
Write preamble
tWPRE
0.25
tCK
Read preamble
CL = 3
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
23
CL = 2
0.5
1.1
0.5
1.1
0.5
1.1
tCK
23
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE to PRECHARGE command
period
tRAS
40
70,000
42
70,000
45
70,000
ns
ACTIVE to ACTIVE command period
tRC
tRAS+
tRP
tRAS+
tRP
tRAS+
tRP
ns
AUTO REFRESH to ACTIVE/AUTO
REFRESH command period
tRFC
72
ns
ACTIVE to READ or WRITE delay
tRCD
15
18
22.5
ns
PRECHARGE command period
tRP
3
tCK
ACTIVE bank A to ACTIVE bank B
delay
tRRD
10
12
15
ns
WRITE recovery time
tWR
15
ns
24
Auto precharge write recovery +
precharge time
tDAL
-
tCK
25
Internal write to Read command delay
tWTR
2
1
tCK
Self Refresh exit to next valid command
delay
tXSR
120
ns
26
Exit power down to next valid command
delay
tXP
2
1
tCK
27
CKE min. pulse width (high and low
pulse width)
tCKE
1
tCK
Refresh Period
tREF
64
ms
Average periodic refresh interval
tREFI
7.8
μs
28,29
MRS for SRR to READ
tSRR
2
tCK
READ of SRR to next valid command
tSRC
CL+1
tCK
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相关代理商/技术参数
参数描述
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