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参数资料
型号： WJLXT386LEB2
厂商： INTEL CORP
元件分类： 数字传输电路
英文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封装： 14 X 14MM, ROHS COMPLIANT, LQFP-100
文件页数： 45/86页
文件大小： 1081K
代理商： WJLXT386LEB2
Datasheet
5
QUAD T1/E1/J1 Transceiver — LXT386
31
E1, G.703 Mask Templates................................................................................. 77
32
T1, T1.102 Mask Templates................................................................................ 78
33
LXT386 Jitter Tolerance Performance ................................................................ 79
34
Jitter Transfer Performance................................................................................. 80
35
Output Jitter for CTR12/13 applications .............................................................. 81
36
60 Plastic Ball Grid Array (PBGA) Package Dimensions .................................... 82
37
100 Pin Low Quad Flat Packages (LQFP) Dimensions ...................................... 83
38
Sample LQFP Non-RoHS Package - Intel
LXT386 Transceiver .......................84
39
Sample LQFP RoHS Package - Intel
LXT386 Transceiver...............................84
40
Order Matrix ........................................................................................................86
Tables
1
Pin Assignments and Signal Descriptions ...........................................................11
2
Line Length Equalizer Inputs............................................................................... 28
3
Jitter Attenuation Specifications .......................................................................... 32
4
Operation Mode Summary .................................................................................. 38
5
Microprocessor Parallel Interface Selection ........................................................ 39
6
Serial and Parallel Port Register Addresses ....................................................... 43
7
Register Bit Names ............................................................................................. 43
8
ID Register, ID (00H)........................................................................................... 44
9
Analog Loopback Register, ALOOP (01H).......................................................... 44
10
Remote Loopback Register, RLOOP (02H) ........................................................ 45
11
TAOS Enable Register, TAOS (03H) ..................................................................45
12
LOS Status Monitor Register, LOS (04H) ...........................................................45
13
DFM Status Monitor Register, DFM (05H) .......................................................... 45
14
LOS Interrupt Enable Register, LIE (06H) ...........................................................45
15
DFM Interrupt Enable Register, DIE (07H).......................................................... 45
16
LOS Interrupt Status Register, LIS (08H)............................................................ 46
17
DFM Interrupt Status Register, DIS (09H)...........................................................46
18
Software Reset Register, RES (0AH)..................................................................46
19
Performance Monitoring Register, MON (0BH)................................................... 46
20
Digital Loopback Register, DL (0CH) ..................................................................46
21
LOS/AIS Criteria Register, LCS (0DH) ................................................................ 46
22
Automatic TAOS Select Register, ATS (0EH)..................................................... 47
23
Global Control Register, GCR (0FH)................................................................... 47
24
Pulse Shaping Indirect Address Register, PSIAD (10H) ..................................... 48
25
Pulse Shaping Data Register, PSDAT (11H) ...................................................... 48
26
Output Enable Register, OER (12H) ................................................................... 48
27
AIS Status Monitor Register, AIS (13H) .............................................................. 48
28
AIS Interrupt Enable Register, AISIE (14H) ........................................................ 49
29
AIS Interrupt Status Register, AISIS (15H) ......................................................... 49
30
TAP State Description ......................................................................................... 51
31
Device Identification Register (IDR) .................................................................... 56
32
Analog Port Scan Register – ASR.......................................................................57
33
Instruction Register – IR...................................................................................... 58
34
Absolute Maximum Ratings................................................................................. 59
35
Recommended Operating Conditions ................................................................. 59
36
DC Characteristics .............................................................................................. 60
37
E1 Transmit Transmission Characteristics.......................................................... 61
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