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| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 25/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Table 12. Additional I/Os
Signal
Pin
Direction
Buffer
MDIO I/O
mdio
mdc
AA4
U1
input/output
input
LVCMOS2
LVCMOS2
Control and Status Signals
reset_n
pwrup_init_en
W1
Y1
input
input
LVCMOS2
LVCMOS2
inj_err_n
1
F5
input
LVCMOS2
ORT82G5 Embedded Core Control, Global I/O and FPGA Con ? guration
I/O
Please refer to the ORCA Series 4 FPGA Data Sheet and the ORT82G5 Data
Sheet for information on the various con?guration options.
Test Points 2
TP0
TP1
TP2
TP3
TP4
AC5
AD1
AF3
AD3
A3
input
input
input/output
output
output
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
1. External pull-up required.
2. I.O that may be used to provide observability of internal signals for debugging pur-
poses. It is recommended that these I/O be routed to accessible points on the PWB.
Table 13 shows voltage bank notations and Table 14 shows pin locations for HSTL1 reference voltages as
assigned for the XGXS IP core.
Table 13. VDDIO for XGXS IP Core - By Bank
Bank
VDDIO0
VDDIO1
VDDIO5
VDDIO6
VDDIO7
VDDIO
2.5V
1.5V
1.5V
2.5V
2.5V
Table 14. V REF for XGXS IP Core - By Bank/Group
Bank/Group
1/2
1/3
1/4
1/5
1/6
5/1
Pin
D21
A26
B21
A18
A15
AL17
V REF
Vref_HSTL1
Vref_HSTL1
Vref_HSTL1
Vref_HSTL1
Vref_HSTL1
Vref_HSTL1
Proper isolation of the V REF pins is critical for proper circuit performance. Please see Lattice technical note TN1036
ORCA ? Series 4 I/O User’s Guide, available on the Lattice web site at www.latticesemi.com, for recommendations
on the proper use of these pins.
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