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参数资料
| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 5/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 3. XGXS Receive Path
xgmii_rxclk_156
PLL
156MHz
PLL
xgmii_rxclk_156_out
DDR
90 °
0 °
RCK78B
Buffer
40b
HDIN[P:N]_BA
xgmii_rx_data[31:0]
xgmii_rx_ctrl[3:0]
XGMII
RX
DDR
SEL
72b@
156MHz
72b@
156MHz
40b
40b
40b
HDIN[P:N]_BB
HDIN[P:N]_BC
HDIN[P:N]_BD
Output
Packet
Checker
XGMII Loopback
(from TX path)
XAUI Loopback
(from TX path)
78MHz
Figure 4. XGXS Receive Direction Data Translations
XAUI Lane 0
Lane 1
Lane 2
Lane 3
XGXS Receive Function
a b c d e f g h i
j
0
0
1 1 1 1 1 X X X properly aligned comma
10b/8b decoding
K A B C D E F G H
XGXS mapping
C 0 1 2 3 4 5 6 7
XGMII
xgmii_rx_data[7:0]
xgmii_rx_ctrl[0]
xgmii_rx_data[15:8]
xgmii_rx_ctrl[1]
xgmii_rx_data[23:16]
xgmii_rx_ctrl[2]
xgmii_rx_data[31:24]
xgmii_rx_ctrl[3]
The transmit path, shown in Figure 5, is the data path from XGMII to XAUI. In the transmit direction, the 36-bit DDR
data and control received at the XGMII are converted to single-edge timing and passed through a slip buffer that
compensates for XAUI and XGMII timing differences. The XGMII data and control are then passed to the TX
encoder, where they are translated and mapped to the 8b/10b XAUI transmission code and then passed to the
SERDES interface.
The transmit direction data translations are shown in Figure 6. Data and control from each of the four XGMII lanes
are translated and mapped to the corresponding XAUI lanes. The transmit encoder includes the transmit idle gen-
eration state machine that generates a random sequence of /A/, /K/ and /R/ code groups as speci ? ed in IEEE
802.3ae.
5
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