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参数资料
| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 34/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
A simulation script ? le is provided in the “eval\simulation” directory for RTL simulation. The script ? le run_eval.bat
uses precompiled models provided with this package. The XGXS design and testbench models have been com-
piled into the work directory in directory “eval\simulation”. The ORCA ORT82G5 and SYSBUS models have been
provided in the directory “eval\lib\modelsim” as tar.gz archives (ort82g5_work.tar.gz and sysbus_work.tar.gz).
These ? les should be unarchived into the directory “eval\lib\modelsim” creating two compiled work directories
“eval\lib\modelsim\ort82g5_work and “eval\lib\modelsim\sysbus_work”.
Simulation Procedures
1. Go to directory “eval\simulation”.
2. Type run_eval.bat
For more information on the use of ModelSim, please refer to the ModelSim User’s Manual. Note that the pre-com-
piled ORT82G5 simulation models provided in this IP evaluation package do not work with the OEM version of
ModelSim embedded in the ispLEVER ? software. The full, licensed version of ModelSim is required to run this sim-
ulation.
Core Implementation
Lattice’s XGXS evaluation package includes a XGXS user application and scripts for synthesizing, mapping and
routing the XGXS IP solution.
The XGXS evaluation package includes the following components:
? Basic XGXS IP core, including SMI and packet generator/checker functions;
? Verilog module that instantiates the ORT82G5 component;
? Verilog module that instantiates the ORCA4 SYSBUS with User Master component, providing a Motorola Power
PC interface to the core’s register interface;
? Verilog module that instantiates the DDR interface components.
This evaluation package is illustrated in Figure 20. The following Verilog ? les are provided:
? xgxs_de ? ne.v for XGXS parameters (Note: This ? le and all IP parameter ? les must not be modi ? ed in any
way. If this ? le is modi ? ed, this IP core may not run at speci ? cation) ;
? xgbe_xgxs_o4_1_002.v for the XGXS core;
? xgmii_io_if.v for the DDR interface;
? ORT82G5_INTF.v for the ORT82G5 module;
? xgxs_sysbus.v for the SYSBUS module;
? xgxs_clk_tx.v for the Tx Clk PLL;
? xgxs_clk_mx2.v for FPGA/FPSC PLLs;
? ring_osc.nmc for a ring oscillator macro to drive um_clk;
? xgxs_top_xgmii.v for top-level module that ties all the application components together.
The XGXS Core is delivered as a gate-level netlist (xgbe_xgxs_o4_1_002.ngo). Note that this ? le and all IP param-
eter ? les must not be modi ? ed in any way. If this ? le is modi ? ed, this IP core may not run at speci ? cation. Users can
compile the entire design shown in Figure 20 to realize a turnkey solution, or instantiate the XGXS Core as a block
box together with any of the other blocks shown and/or their own designs, to realize a unique system-level project.
Users may use xgxs_top_xgmii.v as a template for their own application.
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相关代理商/技术参数 |
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| XGC | 制造商:Excelsys Technologies 功能描述:Power Suply, 36V@5.6A, Open Frame, Cage Mount, Modular, UltiMod Series 制造商:Excelsys Technologies 功能描述:MODULE POWER 28.8V-39.6V 5.6A |
| XGC10-88-S20 | 制造商:Johnson Electric / Saia-Burgess 功能描述:Catalogue / XGC10-88-S20 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC10-88-S20 |
| XGC11-88-S20 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S20 |
| XGC11-88-S20Z1 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S20Z1 |
| XGC11-88-S40 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S40 |
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