参数资料
型号: XGBE-XGXS-O4-N2
厂商: Lattice Semiconductor Corporation
文件页数: 33/38页
文件大小: 0K
描述: IP CORE 10GBE ETHERNET XGXS
标准包装: 1
系列: *
其它名称: XGBEXGXSO4N2
Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
XGXS Core Design Flow
The XGXS IP Core can be implemented using various methods. Figure 19 illustrates the software ? ow model used
when evaluating with the XGXS-XGMII core.
Figure 19. Lattice IP Core Evaluation Flow
Start
Install and launch ispLEVER software
Obtain desired IP package (download
Core Evaluation package or purchase
IP package)
Install IP package
Simulation
Model
Perform functional simulation with
the provided core model
Synthesize top-level design with the
IP black box declaration
Place and route the design
Run static timing analysis
Done
IP Core Netlist
Functional Simulation under ModelSim (PC Platform)
Once the XGXS core has been downloaded and unzipped to the designated directory, the core is ready for evalua-
tion. The RTL simulation environment contains a testbench and a simple application that uses the XGXS design.
The application instantiates the XGXS core, an ORCA ORT82G5 module and an ORCA SYSBUS module. The
module name of the application is called “xgxs_top_xgmii”. The testbench includes a basic XGMII driver, a SMI
driver, and an instantiation of the “xgxs_top_xgmii” application. The SERDES outputs are looped externally back to
the SERDES inputs in this testbench. The XGMII driver sends 25 normal CRPAT packets. The reception of packets
is monitored internally by the pattern monitoring function and is queried using the SMI interface. The XGMII driver
then sends 30 CRPAT packets of which 20 are errored. These are monitored and also queried through the SMI
interface. The SMI interface is used to control the FPSC/FPGA application registers and to query results stored
there and it reports to the ModelSim transcript.
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