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| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 4/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 2. XGXS Solution Simpli?ed Block Diagram
ORT82G5
FPGA
ORT82G5
Embedded
mdc
mdio
xgmii_tx_data[31:0]
MDIO
Interface
XGMII
Array
Core
REFCLK[P:N]_B
HDOUT[P:N]_BA
TX
HDOUT[P:N]_BB
xgmii_tx_ctrl3:0]
xgmii_txclk_156
DDR
Input
SEL
SEL
HDOUT[P:N]_BC
HDOUT[P:N]_BD
Packet
Generator
SERDES
Quad B
Packet
Checker
HDIN[P:N]_BA
xgmii_rx_data[31:0]
XGMII
HDIN[P:N]_BB
xgmii_rx_ctrl[3:0]
xgmii_rxclk_156_out
RX
DDR
Input
Output
SEL
HDIN[P:N]_BC
HDIN[P:N]_BD
xgmii_rxclk_156
Functional Description
The XGXS receive path, shown in Figure 3, is the data path from the XAUI to the XGMII interface. In the receive
direction, 8b/10b encoded data received at the XAUI SERDES interface is demultiplexed and passed to decoder
logic, where it is translated and mapped to the XGMII data format. The output of the encoder is then passed
through a slip buffer that compensates for XAUI and XGMII timing differences and then to the XGMII 36-bit (32-bit
data and four control bits) 156MHz DDR external interface.
The receive direction data translations are shown in Figure 4. The ORT82G5 embedded core aligns the data from
the four SERDES implementing the XAUI lanes and passes the aligned 8b/10b encoded data to the XGXS core
implemented in the programmable array. The 8b/10b symbols on each XAUI lane are converted to XGMII format
and passed to the corresponding XGMII lane.
The XGMII comprises four lanes, labeled [0:3], and one clock in both transmit and receive directions. Each lane
includes eight data signals and one control signal. Double Data Rate (DDR) transmission is utilized, with the data
and control signals sampled on both the rising and falling edges of a 156.25MHz (nom) clock for an effective data
transfer rate of 2.5Gbit/s.
4
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