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| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 32/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 18. Embedded Core <-> Transmit Interface
Note: x = [AA, AB, , BD]
SERDES
BLOCK
MUX BLOCK
8B/10B
ENCODER
10
9
8
DATA BYTE
STBDx[7:0]
K-CONTROL
STBDx[8]
32
4
TWDx[31:0]
TCOMMAx[3:0]
GROUND
STBDx[9]
TSYS_CLK_X
PLL
STBC311x
DIVIDE
BY 4
RWCKx
TCK78(A,B)
4 CHANNELS
TCKSLE[1:0]
MUX
TSYS_CLK[AA,...BD]
EMBEDDED CORE
FPGA
TSYS_CLK[AA,...BD] are inputs to the SERDES quad block A and B respectively from the FPGA. These clocks are
used by each channel to control the timing of the Transmit Data Path. The recommended clocking strategy is to use
TCK78B from the core and feed it to TSYS_CLK_BA, TSYS_CLK_BB, TSYS_CLK_BC and TSYS_CLK_BD.
TCK78[A:B ]
Each of TCK78[A:B] is a muxed output of one of the four clocks operating at up to 78MHz in the embedded core to
the FPGA across the core-FPGA interface. There is one clock output per SERDES quad block. TCK78B is wired to
TSYS_CLK_[BA-BD]. For the XGXS IP core, the TCK78B mux should be set such that TCK78B is supplied by the
clock source for channel BA.
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