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参数资料
| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 37/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Place and Route
Once the EDIF netlist is generated, the next step is to map, place and route the design. To map, place and route
the entire XGXS solution in one step, Go to the directory “par\orca4\con ? g1” and type runpar.bat. This script will
process the EDIF ? le to map, place and route the XGXS IP solution.
The step-by-step procedure provided below may also be followed. Note that results may vary from those obtained
with the scripted run due to small differences in options.
Once the EDIF netlist is generated, import the EDIF into the Project Navigator. The ispLEVER software automati-
cally detects the provided EDIF netlist of the instantiated IP core in the design. The step-by-step procedure pro-
vided below describes how to perform Place and Route in ispLEVER for an ORCA device:
1. Create a new working directory for Place and Route.
2. Start a new project, assign a project name and select the project type as EDIF.
3. Select the ORT82G5 target device, with -3 speed grade and BM680 package.
4. Copy the following ? les to the Place and Route working directory:
a) eval\par\xgbe_xgxs_o4_1_002.ngo
b) eval\par\xgxs_top_exemplar.prf if the EDIF was generated using LeonardoSpectrum or
eval\par\xgxs_top_synplicity.prf if the EDIF was generated using Synplicity Synplify
c) eval\source\ring_osc.nmc
d) The top-level EDIF netlist generated from running synthesis
5. Rename the .prf ? le (in step 4) to match the project name. For example, if the project name is “demo”, then the
.prf ? le must be renamed to demo.prf. The preference ? le name must match that of the project name.
6. Import the EDIF netlist into the project.
7. In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options. The Timing Checkpoint Options
window will pop-up. In both Checkpoint Options, select Continue.
8. In the ispLEVER Project Navigator, highlight Place & Route Design, with a right mouse click select Properties.
Set the following Properties:
? Placement Iterations: 1
? Placement Save Best Run: 1
? Placement Iteration Start Point: 1 if the EDIF was generated using Synplify, or 1 if the EDIF was generated using
LeonardoSpectrum
? Routing Resource Optimization: 1
? Routing Delay Reduction Passes: 6
? Routing Passes: 25
? Placement Effort Level: 5
All other options remain at their default values.
9. Select the Place & Route Trace Report in the project navigator to execute Place and Route and generate a tim-
ing report for ORCA.
10. Highlight Place & Route TRACE Report, with a right mouse click and select Force One Level. A new timing
report is generated.
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相关代理商/技术参数 |
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| XGC10-88-S20 | 制造商:Johnson Electric / Saia-Burgess 功能描述:Catalogue / XGC10-88-S20 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC10-88-S20 |
| XGC11-88-S20 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S20 |
| XGC11-88-S20Z1 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S20Z1 |
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